Intel PXA26X - Manual (Page 105)

Intel® PXA26x Processor Family Developer’s Manual 3-39
Clocks and Power Manager
3.6.3 Oscillator Configuration Register (OSCC)
The OSCC, refer to Table 3-23 , controls the 32.768-KHz oscillator configuration. It contains two
bits, the set-only 32.768-KHz OON and the read-only 32.768-KHz OOK. The OON bit enables the
external 32.768-KHz oscillator and can only be set by software. When the oscillator is enabled, it
takes up to 10 seconds to stabilize. When the oscillator is stabilized, the processor sets the OOK bit.
When the OOK bit is set, the RTC and power manager are clocked from the 32.768-KHz oscillator.
Otherwise, the 3.6864-MHz oscillator is used. The OPDE bit, which allows the 3.6864-MHz
oscillator to be disabled in sleep mode, is ignored (treated as if it were clear) if the OOK bit is clear.
OOK can only be reset by hardware reset.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
3.6.4 Clocks Manager Register Locations
Table 3-24 shows the registers associated with the clocks manager and the physical addresses used
to access them.
Table 3-23. OSCC Bit Definitions
0x4130_0008 OSCC Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
OO
N
OO
K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] — Reserved
1 OON
32.768-KHz OON (write-once only bit):
0 – 32.768-KHz oscillator is disabled. The 3.6864-MHz oscillator (divided by 112) clocks
the real time clock and power manager.
1 – 32.768-KHz oscillator is enabled. OON can not be cleared once written except by
hardware reset.
Cleared by hardware reset.
0 OOK
32.768-KHz OOK (read-only bit):
0 – 32.768-KHz oscillator is disabled or not stable. The 3.6864-MHz oscillator (divided by
112) clocks the real time clock and power manager.
1 – 32.768-KHz oscillator has been enabled (OON=1) and stabilized. It will clock the real
time clock and power manager.
Cleared by hardware reset.
Table 3-24. Clocks Manager Register Locations
Address Name Description
0x4130 0000 CCCR Core Clock Configuration Register
0x4130 0004 CKEN Clock Enable Register
0x4130 0008 OSCC Oscillator Configuration Register