Intel PXA26X - Manual (Page 231)

Intel® PXA26x Processor Family Developer’s Manual 6-41
Memory Controller
• nADV assert time = 3 MEMCLKs
• MA, nCS setup to nADV asserted = 1 MEMCLK
• nADV deasserted to nOE asserted = (Code * 2) – 4 MEMCLKs
6.8 Asynchronous Static Memory
6.8.1 Static Memory Interface
The Static Memory interface is made up of six chip selects: nCS[5:0]. The chip selects can be
configured as the following:
• Non-burst ROM or flash memory
• Burst ROM or flash
• SRAM
• SRAM-like variable latency I/O devices
The Variable Latency I/O interface differs from SRAM in that it allows the use of the data-ready
input signal, RDY, to insert a variable number of memory-cycle wait states. The data bus width for
each chip-select region can be programmed as 16- or 32-bit. nCS[3:0] can also be configured for
synchronous static memory (refer to
Section 6.7, “Synchronous Static Memory Interface” on
page 6-30 ). During variable latency I/O writes, nPWE is used instead of nWE so SDRAM
refreshes can be executed while performing the VLIO transfers.
The use of the signals nOE, nWE, and nPWE is summarized below:
• nOE is asserted for all reads
• nWE is asserted for flash and SRAM writes
• nPWE is asserted for Variable Latency I/O writes
For SRAM and variable latency I/O implementations, DQM[3:0] signals are used for the write byte
enables, where DQM[3] corresponds to the MSB. The processor supplies 26-bits of byte address
for access of up to 64 Mbytes per chip select. This byte address is sent out on the 26 external
address pins. Do not connect MA[1:0] for 32-bit systems. Do not connect MA[0] for 16-bit
systems (the PXA26x processor family operating in 16-bit mode). For all reads on a 32 bit system
DQM[3:0] and MA[1:0] are 0. For all reads on a 16-bit system DQM[1:0] and MA[0] are 0. In the
timing diagrams, these byte addresses are shown and referred to as addr.
Table 6-20. 32-Bit Bus Write Access (Sheet 1 of 2)
Data Size MA[1:0] DQM[3:0]
8 bit 00 1110
8 bit 01 1101
8 bit 10 1011
8 bit 11 0111