Intel PXA26X - Manual (Page 487)

Intel® PXA26x Processor Family Developer’s Manual 13-25
AC97 Controller Unit
13.8.3.6 PCM-Out Status Register (POSR)
13.8.3.7 PCM_In Status Register (PISR)
Table 13-12. PCM-Out Status Register
Physical Address
4050_0010
POSR Register AC97
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FIFO
E
R
eser
ved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — Reserved
4 FIFOE
FIFO ERROR (FIFOE):
0 – No transmit FIFO errors have occurred
1 – A transmit FIFO error occurred. This bit is set if a transmit FIFO underrun occurs. In
this case, the last valid sample is repetitively sent out and the pointers are not
incremented.This could happen due to:
1. No more valid buffer data available for transmits.
2. Buffer data available but DMA controller has excessive bandwidth requirements.
Bit is cleared by writing a 1 to this bit position.
3:0 — Reserved
Table 13-13. PCM_In Status Register
Physical Address
4050_0014
PISR Register AC97
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FIFO
E
R
eser
ved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — Reserved
4 FIFOE
FIFO ERROR (FIFOE):
0 – No receive FIFO error has occurred.
1 – A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this
case, the FIFO pointers don't increment, the incoming data from the AC-link is not
written into the FIFO and the incoming data is lost. This could happen due to DMA
controller having excessive bandwidth requirements and hence not being able to flush
out the receive FIFO in time.
Bit is cleared by writing a 1 to this bit position.
3:0 — Reserved