Intel PXA26X - Manual (Page 399)

Intel® PXA26x Processor Family Developer’s Manual 11-5
Fast Infrared Communication Port
11.2.7 Baud Rate Generation
The baud rate is derived by dividing a fixed 48-MHz clock by six. Using a digital PLL, the 8-MHz
baud (or timeslot) clock for the receive logic is synchronized with the 4PPM data stream each time
a transition is detected on the receive data line. To encode a 4-Mbps data stream, the required chip
frequency is 2.0 MHz, with four timeslots per chip at a frequency of 8.0 MHz. Receive data is
sampled halfway through each timeslot period by counting three of the six 48-MHz clock periods
that make up each timeslot (see
Figure 11-2 ). The chips are synchronized during the reception
preamble. The pattern of four chips repeated 16 times is used to identify the first timeslot (or the
beginning of a chip) and resets the 2-bit timeslot counter logic.
11.2.8 Receive Operation
The IrDA standard specifies that all transmission occurs at half-duplex. This restriction forces
software to enable one direction at a given time. Either the transmit or receive logic can be enabled,
but not both. The FICP’s hardware does not impose such a restriction.The software can enable both
the transmitter and receiver. This feature is used with the FICP’s loopback mode, which internally
connects the output of the transmit serial shifter to the input of the receive serial shifter.
After the FICP is enabled, the receiver logic begins and selects an arbitrary chip boundary, uses a
serial shifter to receive four incoming 4PPM chips from the receive data pin, and latches and
decodes the chips one at a time. If the chips do not have the correct preamble, the timeslot
counter’s clock skips one 8-MHz period and effectively delays the timeslot count by one. This
process is called hunt mode and is repeated until the chips have the correct preamble, which
indicates that the timeslot counter is synchronized. The preamble can be repeated as few as 16
times or can be continuously repeated to indicate an idle transmit line.
After 16 preambles are transmitted, the start flag is received. The start flag is eight chips long. If
any portion of the start flag does not match the encoding, the receive logic signals a framing error
and the receive logic returns to hunt mode.
When the correct start flag is recognized, each following group of four chips is decoded into a data
byte and placed in a 5-byte temporary FIFO that is used to prevent the CRC from being placed in
the receive FIFO. When the temporary FIFO is full, data values are transferred to the receive FIFO
one at a time. A frame’s first data byte is the address. If receiver address matching is enabled, the
received address is compared to the address in the address match value field in ICCR1. If the
values match or the incoming address contains all ones, all following data bytes, including the
address byte, are stored in the receive FIFO. If the values do not match, the receiver logic does not
store any data in the receive FIFO, ignores the remainder of the frame, and searches for the next
preamble. If receiver address matching is not enabled, the frame’s first data byte is stored in the
FIFO as normal data. The frame’s second data byte can contain an optional control field and must
be decoded in software.
The IrDA standard limits frames to any amount of data up to a 2047 bytes (including the address
and control bytes). The FICP does not limit frame size. Software must ensure that each incoming
frame does not exceed 2047 bytes.
When the receive FIFO reaches its trigger level, an interrupt (if enabled) and DMA transfer request
(if no errors are detected in the data) are signalled. If the data is not removed quickly enough to
prevent the FIFO from completely filling, the receive logic attempts to place additional data into
the full FIFO and an overrun error is signalled. When the FIFO is full, all subsequent data bytes
received are lost and all FIFO contents remain intact.