3 servicing an interrupt, 5 channel states, 6 read and write order – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
5-9
Direct Memory Access Controller
5.1.4.3
Servicing an Interrupt
If software receives an interrupt caused by a successful descriptor fetch, i.e. DCSRx[STARTINTR]
= 0b1, then software must write a 1 to this bit to reset the corresponding interrupt. Software
normally accomplishes this by reading the DCSRx register, modifying the data value by setting the
DCSRx[STARTINTR]=0b1 and leaving the DCSRx[RUN] bit set, and then writing this modified
value back to the DCSRx. If the channel stops, DCSRx[RUN] = 0b0, before writing this value back
to the DCSRx, then software can inadvertently set the DCSRx[RUN] bit before properly
configuring other DMA registers. In order to avoid this problem, after writing the modified value
back to the DCSRx, software must read the DCSRx and check to see if DCSRx[RUN] and
DCSRx[STOPSTATE] are both set. If they are, then software must clear the DCSRx[RUN] bit and
re-initialize the DMA channel.
5.1.5
Channel States
A DMA channel can go through any of the following states:
•
Uninitialized: Channel is in an uninitialized state after reset.
•
Valid Descriptor, Not Running: Software has loaded a descriptor in the DDADR of the
channel, in the descriptor fetch mode, or has programmed DSADR, DTADR and DCMD
values, in no-descriptor fetch mode, but the corresponding run bit in the DCSR[RUN] register
is not set to a 1.
•
Descriptor Fetch, Running: Fetching four words of descriptors from the memory.
•
Wait for Request: Channel is waiting for a request before it starts to transfer the data.
•
Transfer Data: Channel is transferring data.
•
Channel Error: Channel has an error. It remains in the stopped state until software clears the
error condition, re-initializes the channel, and writes a 1 to the DCSR[RUN] bit. See
and
for details.
•
Stopped: Channel is stopped.
and
show the progression from state to state.
5.1.6
Read and Write Order
The DMAC does not ensure the order of programmed I/O reads and writes made from the
processor to the I/O devices (including the on-chip I/O devices). Software must ensure the order.
The DMAC ensures that all memory references made by a single DMA data stream are presented
to main memory in the order in which they were made. The descriptor fetches occurs between the
data blocks. This allows self-modifying DMA descriptor chains to function correctly (see
). It also allows schemes in which a DMA stream writes data blocks followed by
status blocks and schemes in which another DMA stream (probably from the processor) polls the
same field in the status block.
The DMAC ensures that data is not retained in per-channel buffers between descriptors. When a
descriptor is completely processed, any read data that is buffered in the channel is discarded and
any write data that is buffered in the channel is sent to memory (although it may not be there yet).
The DMA interrupt is not posted until the descriptor is completely processed.