Intel PXA26X - Manual (Page 398)

11-4 Intel® PXA26x Processor Family Developer’s Manual
Fast Infrared Communication Port
11.2.3 Address Field
A transmitter uses the 8-bit address field to target a receiver when multiple stations are connected
to the same set of serial lines. The address allows up to 255 stations to be uniquely addressed (0x00
to 0xFE). The broadcast address 0xFF is used to send messages to all of the connected stations.
For reception, FICP control register 1 (ICCR1) is used to program a unique receive address. The
AME bit in the FICP control register 0 (ICCR0) determines the address match function. The
received frames’ addresses are stored in the receive FIFO with normal data.
11.2.4 Control Field
The control field is an optional 8-bit field that is defined by software. The FICP does not provide
hardware decode support for the control byte. It treats all bytes between the address and the CRC as
data.
11.2.5 Data Field
The data field can have a length from 0 to 2045 bytes. Application requirements and target
system’s transmission characteristics affect the data field’s length. Software must determine the
length of the data to maximize the amount that can be transmitted in each frame while allowing the
CRC to detect all errors during transmission. The serial port does not contain hardware that
restricts the maximum amount of data that can be transmitted or received. If a data field that is not
a multiple of eight bits is received, an abort is signalled.
11.2.6 CRC Field
The FICP uses a 32-bit cyclic redundancy check (CRC) to detect bit errors that occur during
transmission. The CRC is generated from the address, control, and data fields, and is included in
each frame. Transmit and receive logic have separate CRC generators. The CRC computation logic
is set to all ones before each frame is transmitted or received and the result is inverted before it is
used for comparison or transmission. The transmitter calculates a CRC as data is transmitted and
places the inverse of the resulting 32-bit value at the end of each frame until the stop flag is
transmitted. The receiver also calculates a CRC and inverts it for each data frame that it receives.
The receiver compares the calculated CRC to the expected CRC value at the end of each frame.
If the calculated value does not match the expected value, the CRC error bit that corresponds to the
last data byte received is set. When this byte reaches the trigger level range, an interrupt is
generated.
Note: Unlike the address, control, and data fields, the 32-bit inverted CRC value is transmitted and
received most significant nibble first.
The cyclic redundancy checker uses the 32-term polynomial:
CRC x
( )
x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 x5 x4 x2 x 1 + + + + + + + + + + + + + +
( )
=