Intel PXA26X User Manual
Page 4
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Intel® PXA26x Processor Family Developer’s Manual
Contents
3
Clocks and Power Manager .........................................................................................................3-1
3.1
Clock Manager Introduction...............................................................................................3-1
3.2
Power Manager Introduction..............................................................................................3-2
3.3
Clock Manager...................................................................................................................3-2
3.3.1
32.768-KHz Oscillator...........................................................................................3-4
3.3.2
3.6864-MHz Oscillator ..........................................................................................3-4
3.3.3
Core Phase Locked Loop .....................................................................................3-4
3.3.4
95.85-MHz Peripheral Phase Locked Loop ..........................................................3-5
3.3.5
147.46-MHz Peripheral Phase Locked Loop ........................................................3-6
3.3.6
Clock Gating .........................................................................................................3-6
3.4
Resets and Power Modes..................................................................................................3-6
3.4.1
Hardware Reset....................................................................................................3-7
3.4.2
Watchdog Reset ...................................................................................................3-7
3.4.3
GPIO Reset ..........................................................................................................3-8
3.4.4
Run Mode .............................................................................................................3-9
3.4.5
Turbo Mode ..........................................................................................................3-9
3.4.6
Idle Mode ............................................................................................................3-10
3.4.7
33-MHz Idle Mode ..............................................................................................3-12
3.4.8
Frequency Change Sequence ............................................................................3-13
3.4.9
Sleep Mode.........................................................................................................3-15
3.4.10 Power Mode Summary .......................................................................................3-20
3.5
Power Manager Registers ...............................................................................................3-22
3.5.1
Power Manager Control Register (PMCR) .........................................................3-23
3.5.2
Power Manager General Configuration Register (PCFR)...................................3-24
3.5.3
Power Manager Wake-Up Enable Register (PWER)..........................................3-25
3.5.4
Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-26
3.5.5
Power Manager Falling-Edge Detect Enable Register (PFER) ..........................3-27
3.5.6
Power Manager GPIO Edge Detect Status Register (PEDR).............................3-28
3.5.7
Power Manager Sleep Status Register (PSSR) .................................................3-29
3.5.8
Power Manager Scratch Pad Register (PSPR) ..................................................3-30
3.5.9
Power Manager Fast Sleep Wake Up Configuration Register (PMFWR)...........3-31
3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........3-31
3.5.11 Reset Controller Status Register (RCSR)...........................................................3-33
3.5.12 Power Manager Register Locations....................................................................3-34
3.6
Clocks Manager Registers...............................................................................................3-35
3.6.1
Core Clock Configuration Register (CCCR) .......................................................3-35
3.6.2
Clock Enable Register (CKEN)...........................................................................3-37
3.6.3
Oscillator Configuration Register (OSCC) ..........................................................3-39
3.6.4
Clocks Manager Register Locations ...................................................................3-39
3.7
Coprocessor 14: Clock and Power Management ............................................................3-40
3.7.1
Core Clock Configuration Register (CCLKCFG).................................................3-40
3.7.2
Power Mode Register (PWRMODE)...................................................................3-41
3.8
External Hardware Considerations ..................................................................................3-41
3.8.1
Power-On-Reset Considerations ........................................................................3-41
3.8.2
Driving the Crystal Pins from an External Clock Source.....................................3-41
3.8.3
Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-42
4
System Integration Unit ................................................................................................................ 4-1
4.1
General-Purpose Input/Output...........................................................................................4-1
4.1.1
GPIO Operation ....................................................................................................4-1