2 receive fifo errors, 2 interrupts, 3 registers – Intel PXA26X User Manual
Page 480: D in, Section 13.8.3
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Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
13.8.1.2
Receive FIFO Errors
Channel-specific status bits are updated during receive overrun conditions and trigger interrupts
when enabled. Refer to
Table 13-13, “PCM_In Status Register”
, and
Table 13-22, “Modem-In Status Register”
for details regarding the status bits.
During receive over-run conditions, data that the codec sends is not recorded.
13.8.2
Interrupts
The following status bits interrupt the processor when the interrupts are enabled:
•
Mic-in FIFO error – Mic-in receive FIFO’s over-run or under-run error.
•
Modem-in FIFO error – Modem receive FIFO’s over-run or under-run error.
•
PCM-in FIFO error – Audio receive FIFO’s over-run or under-run error.
•
Modem-out FIFO error – Modem transmit FIFO’s over-run or under-run error.
•
PCM-out FIFO error – Audio transmit FIFO’s over-run or under-run error.
•
Modem codec GPI status change interrupt – Interrupts the CPU if bit 0 of slot 12 is set. This
indicates a change in one of the bits in the modem codec’s GPIO register.
•
Primary codec resume interrupt – Sets a status register bit when the primary codec resumes
from a lower power mode. Software writes a 1 to this bit to clear it.
•
Secondary Codec resume interrupt – Sets a status register bit when the secondary codec
resumes from a lower power mode. Software writes a 1 to this bit to clear it.
•
Codec command done interrupt – Interrupts the CPU when a codec register’s command is
completed. Software writes a 1 to this bit to clear it.
•
Codec status done interrupt – Interrupts the CPU when a codec register’s status address and
data reception are completed. Software writes a 1 to this bit to clear it.
•
Primary codec ready interrupt – Sets a status register bit when the primary codec is ready. The
codec sets bit 0 of slot 0 on the input frame to signal that it is ready. Software clears the
GCR[PRIRDY_IEN] bit to clear this interrupt.
•
Secondary codec ready interrupt – Sets a status register bit when the secondary codec is ready.
The codec sets bit 0 of slot 0 on the input frame to signal that it is ready. Software clears the
GCR[SECRDY_IEN] bit to clear this interrupt.
13.8.3
Registers
The ACUNIT and codec registers are mapped in addresses ranging from 0x4050_0000 through
0x405F_FFFF. All ACUNIT registers are 32-bit addressable. Though a codec has up to sixty-four
16-bit registers that are 16-bit addressable they are accessed via 32-bit address map and translated
to 16-bit for the codec.
The programmed I/O and DMA bursts can access the following registers:
•
Global registers – The ACUNIT has three global registers: status, control, and codec access
registers that are common to the audio and modem domains.
•
Channel-specific audio ACUNIT registers refer to PCM-out, PCM-in, and mic-in channels.
•
Channel-specific Modem ACUNIT registers refer to modem-out and modem-in channels.