Intel PXA26X - Manual (Page 413)

Intel® PXA26x Processor Family Developer’s Manual 12-3
Universal Serial Bus Device Controller
Data flow is relative to the USB host. IN packets represent data flow from the UDC to the host.
OUT packets represent data flow from the host to the UDC.
The FIFOs for the bulk and isochronous endpoints are double-buffered so one packet can be
processed as the next is assembled. While the UDC transmits an IN packet from a particular
endpoint, the core can load the same endpoint for the next frame transmission. While the core
unloads an OUT endpoint, the UDC can continue to process the next incoming packet to that
endpoint.
12.3 Universal Serial Bus Protocol
After a core reset or when the USB host issues a USB reset, the UDC configures all endpoints and
is forced to use the USB default address, zero. After the UDC configures the endpoints, the host
assigns the UDC a unique address. At this point, the UDC is under the host’s control and responds
to commands that use control transactions to transmit to endpoint 0.
12.3.1 Signalling Levels
USB uses differential signalling to encode data and to indicate various bus conditions. The USB
specification refers to the J and K data states to differentiate between high- and low-speed
transmissions. Because the UDC supports only 12 Mbps transmissions, references are only made to
actual data state zero and actual data state 1.
By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct
states are represented. Two of the four states represent data. A 1 indicates that UDC+ is high and
UDC- is low. A zero indicates that UDC+ is low and UDC- is high. The two remaining states and
pairings of the four encodings are further decoded to represent the current state of the USB.
Table 12-2 shows how differential signalling represents eight different bus states.
Hosts and hubs have pull-down resistors on both the D+ and D- lines. When a device is not
attached to the cable, the pull-down resistors cause D+ and D- to be pulled down below the single-
ended low threshold of the host or hub. This creates a state called single-ended zero (SE0). The
Table 12-2. USB States
Bus State UDC+/UDC- Pin Levels
Idle UDC+ high, UDC- low (same as a 1).
Suspend Idle state for more than 3 ms.
Resume UDC+ low, UDC- high (same as a 0).
Start of Packet Transition from idle to resume.
End of Packet UDC+ AND UDC- low for 2 bit times followed by an idle for 1 bit time.
Disconnect
UDC+ AND UDC- below single-ended low threshold for more than 2.5 µs.
(Disconnect is the static bus condition that results when no device is plugged into a hub
port.)
Connect UDC+ OR UDC- high for more than 2.5 µs.
Reset
UDC+ AND UDC- low for more than 2.5 µs. (Reset is driven by the host controller and
sensed by a device controller.)