Intel PXA26X - Manual (Page 51)

Intel® PXA26x Processor Family Developer’s Manual 2-21
System Architecture
2.13 Register Address Summary
Table 2-8 lists the registers present in the PXA26x processor family.
Table 2-7. Pin Description Notes
Note Description
[1]
GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins
are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input
paths must be enabled and the pull-ups turned off
by clearing the Read Disable Hold (RDH) bit described in
Section 3.5.7, “Power Manager Sleep Status Register” on page 3-27 . Even though sleep mode sets the RDH bit,
the pull-up resistors are not re-enabled by sleep mode. The exact value of the internal pull-up resistor cannot be
guaranteed; always use an external pull-up for signals that require pull-ups.
[2]
Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to
Section 3.3, “Clock Manager” on page 3-2 for details on sleep mode operation.
[3]
GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the
corresponding PGSRn. See
Section 3.5.9, “Power Manager GPIO Sleep State Registers” and Section 4.1.3.2,
“GPIO Pin Direction Registers (GPDR)” on page 4-6 . If selected as an input, this pin does not drive during sleep.
If selected as an output, the value contained in the Sleep State Register is driven out onto the pin and held there
while the PXA26x processor family is in sleep mode.
GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
[4]
Static Memory Control Pins: During sleep mode, these pins can be programmed to either drive the value in
the Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the
Power Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these
pins function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high
by the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.
[5]
PCMCIA Control Pins: During sleep mode: Can be programmed either to drive the value in the Sleep State
Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during
the transition to sleep these pins function as described in [3], above.
[6] During sleep, this supply must be driven low to conserve power.
[7] Remains powered in sleep mode.
[8]
There are four GPIO pins on the PXA26x processor family that do not default to GPIOs out of reset. Instead,
these four pins, nSDCS[3:2], RDnWR, nACRESET, default to their alternate function. During sleep, if the pins
are configured or left in their alternate function, their sleep state is as shown in the table above. If the pins are
configured as GPIOs, their sleep state is determined similar to other GPIOs (See Note[3]); however, on sleep
exit they default to their alternate function and the state after sleep exit is determined by their alternate function.
See
Section 4.1, “General-Purpose I/O” for more information.
Table 2-8. Register Address Summary (Sheet 1 of 13)
Unit Address Register Symbol Register Description
DMA
Controller
0x4000 0000
0x4000 0000 DCSR0 DMA Control / Status Register for Channel 0
0x4000 0004 DCSR1 DMA Control / Status Register for Channel 1
0x4000 0008 DCSR2 DMA Control / Status Register for Channel 2
0x4000 000C DCSR3 DMA Control / Status Register for Channel 3
0x4000 0010 DCSR4 DMA Control / Status Register for Channel 4
0x4000 0014 DCSR5 DMA Control / Status Register for Channel 5
0x4000 0018 DCSR6 DMA Control / Status Register for Channel 6