Intel PXA26X - Manual (Page 420)

12-10 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
12.3.7 Configuration
In response to the GET_DESCRIPTOR command, the user device sends back a description of the
UDC configuration. The UDC can physically support more data channel bandwidth than the USB
specification allows. When the device responds to the host, it must specify a legal USB
configuration. For example, if the device specifies a configuration of six isochronous endpoints of
256 bytes each, the host is not able to schedule the proper bandwidth and does not take the UDC
out of configuration 0. The user device determines which endpoints to report to the host. If an
endpoint is not reported, it is not used. Another option, attractive for use with isochronous
endpoints, is to describe a configuration of a packet with a maximum size less than 256 bytes to the
host. For example, if software responds to the GET_DESCRIPTOR command that endpoint 3 only
supports 64 bytes maximum packet isochronous IN data, the user device must set the
UDCCS3[TSP] bit after it loads 64 bytes for transmission. Similarly, if endpoint 4 is described as
supporting 128 bytes maximum packet isochronous OUT data, the UDC recognizes the end of the
packet, sets UDCCS4[RPC], and an interrupt is generated.
The direction of the endpoints is fixed. Physically, the UDC only supports interrupt endpoints with
a maximum packet size of 8 bytes or less, bulk endpoints with a maximum packet size of 64 bytes
or less, and isochronous endpoints with a maximum packet size of 256 bytes or less.
To make the processor more adaptable, the UDC supports a total of four configurations. Each of
these configurations are identical in the UDC, software can make three distinct configurations,
each with two interfaces. Configuration 0 is a default configuration of endpoint 0 only and cannot
be defined as any other arrangement.
After the host completes a SET_CONFIGURATION or SET_INTERFACE command, the
software must decode the command to empty the OUT endpoint FIFOs and allow the core to set up
the proper power/peripheral configurations.
12.4 UDC Hardware Connection
This section explains how to connect the USB interface for a variety of devices.
12.4.1 Self-Powered Device
Figure 12-2 shows how to connect the USB interface for a self-powered device. The 0
Ω
resistors
are optional and if they are not used, USB D+ must connect directly to the device UDC D+ and
connect USB D- must connect directly to the device UDC D-. The UDC D+ and UDC D- pins are
designed to match the impedance of a USB cable, 90
Ω
, without external series resistors. To allow
minor impedance corrections to compensate for the impedance that results from the board trace,
0
Ω
resistors are recommended on the board.
A 5 V to 3.3 V device is required because the input pins of the processor can only tolerate 3.3 V.
The device can be implemented in a number of ways. The most robust and expensive solution is a
power-on-reset device such as a MAX6348. This solution produces a clean signal edge and
minimizes signal bounce. A more inexpensive solution is a 3.3 V line buffer with inputs that can
tolerate 5 V. This solution does not reduce signal bounce, so software must compensate by reading
the GPIO repeatedly until it proves to be stable. A third solution is a signal bounce minimization
circuit that can tolerate 5 V but produces a 3.3 V signal to the GPIO pin.