Intel PXA26X - Manual (Page 414)

12-4 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
host detects a disconnect when an SE0 persists for more than 2.5 µs (30 bit times). When the UDC
is connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be pulled above
the single-ended high threshold level. After 2.5 µs, the host detects a connect.
After the host detects a connect, the bus is in the Idle state because UDC+ is high and UDC- is low.
The bus transitions from the Idle state to the resume state (a 1 to 0 transition) to signal the start of
packet (SOP). Each USB packet begins with a sync field that starts with the 1-to-0 transition (see
Section 12.3.1, “Signalling Levels” on page 12-3 ). After the packet data is transferred, the bus
signals the end of packet (EOP) state by pulling both UDC+ and UDC- low for 2 bit times followed
by an idle state for 1 bit time. If the idle persists for more than 3 ms, the UDC enters suspend state
and is placed in low-power mode. The host can awaken the UDC from the suspend state by
signalling a reset or by switching the bus to the resume state via normal bus activity. Under normal
operating conditions, the host periodically signals an start of frame (SOF) to ensure that devices do
not enter the suspend state.
12.3.2 Bit Encoding
USB uses nonreturn to zero inverted (NRZI) to encode individual bits. Both the clock and the data
are encoded and transmitted in the same signal. Data is represented by transitions rather than by the
signal’s state. A zero is represented by a transition, and a one is represented by no transition, which
produces the data. Each time a zero occurs, the receiver logic synchronizes the baud clock to the
incoming data, which produces the clock. To ensure the receiver is periodically synchronized, six
consecutive ones in the serial bit stream trigger the transmitter to insert a zero. This procedure is
known as bit stuffing. The receiver logic detects stuffed bits and removes them from incoming
data. Bit stuffing causes a transition on the incoming signal at least once every 7 bit times to ensure
the baud clock is locked. Bit stuffing is enabled for an entire packet from the time the SOP is
detected until the EOP is detected (enabled during the sync field through the CRC field).
Figure 12-1 shows the NRZI encoding of the data byte 0b1101 0010.
12.3.3 Field Formats
Individual bits are assembled into groups called fields. Use fields to construct packets and packets
to construct frames or transactions. There are seven USB field types: sync, PID, address, endpoint,
frame number, data, and CRC.
A sync is preceded by the idle state and is the first field of every packet. The first bit of a sync field
signals the SOP to the UDC or host. A sync is 8 bits wide and consists of seven zeros followed by
a one (0x80). Bits are transmitted to the bus least significant bit first in every field, except the CRC
field.
Figure 12-1. NRZI Bit Encoding Example