3 dma request to channel map registers – Intel PXA26X User Manual
Page 177
Intel® PXA26x Processor Family Developer’s Manual
5-19
Direct Memory Access Controller
5.3.3
DMA Request to Channel Map Registers
The read/write DMA Request to Channel Map Registers (DRCMRx) (
) map each DMA
request to a channel. Refer to
for details.
3
STOPSTATE
STOP STATE (read-only):
0 – Channel is running
1 – Channel is in uninitialized or stopped state.
If the channel is in the uninitialized or stopped state, this status bit is set. If the
DCSR[STOPIRQEN] is set to 1, the DMAC generates an interrupt. Channel States are
described in
Section 5.1.5, “Channel States” on page 5-9
.
Software must reprogram the DDADRx and write a 1 to the DCSR[RUN] bit to restart the
channel and clear this bit.
Software must write a 0 to the DCSR[STOPIRQEN] bit to reset the interrupt
2
ENDINTR
END INTERRUPT (read / write):
0 – No interrupt
1 – Interrupt caused because the current transaction was successfully completed and
DCMD[LENGTH] = 0.
DCMD[ENDIRQEN] bit must be set for an interrupt to occur. Software must write a 1 to this
bit to reset the corresponding interrupt. Writing a 0 to this bit has no effect.
1
STARTINTR
START INTERRUPT (read / write):
0 – No interrupt
1 – Interrupt caused due to successful descriptor fetch
DCMD[STARTIRQEN] bit must be set for an interrupt to occur. Software must write a 1 to
this bit to reset the corresponding interrupt. Writing a 0 to this bit has no effect.
0
BUSERR
INTR
BUS ERROR INTERRUPT (read / write):
0 – No interrupt
1 – Bus error caused interrupt
Indicates that there was an error while transferring data. An error during data transfer
occurs when the channel has a bad descriptor, source, or target address. An address is
considered bad when it points to a non-busable location or reserved space. Software must
write a 1 to this bit to reset the corresponding interrupt. Writing a 0 to this bit has no effect.
Only one error incidence per channel is logged. The channel that caused the error is
updated at the end of the transfer and is accessible after it logs an error until it is
reprogrammed and the corresponding run bit is set.
Table 5-7. DMA Channel Control/Status Register Bitmap and Bit Definitions (Sheet 2 of 2)
Physical Address
0x4000_0000 - 0x4000_003C
DMA Channel Control/Status
Register (DCSRx)
DMA
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RU
N
NO
DE
SCF
E
T
C
H
STO
P
IRQ
E
N
RESERVED
R
E
Q
PEN
D
RESERVED
STO
P
S
T
A
T
E
E
NDI
N
T
R
ST
A
R
TIN
T
R
BU
SER
RI
N
T
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description