Intel PXA26X - Manual (Page 408)

11-14 Intel® PXA26x Processor Family Developer’s Manual
Fast Infrared Communication Port
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11.3.6 FICP Status Register 1
FICP status register 1 (ICSR1) contains flags that indicate that the receiver is synchronized, the
transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and that an EOF,
CRE, or underrun error has occurred. All bits in ICSR1 are read-only.
Table 11-6. Fast Infrared Communication Port Status Register 0
0x4080 0014
Fast Infrared Communication
Port Status Register 0 (ICSR0)
FICP
Bit
3
1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0
9 8 7 6 5 4 3 2 1 0
R
eser
ved
FR
E
RF
S
TFS RA
B
TU
R
EI
F
Rese
t
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
[31:6] — Reserved
5 FRE
FRAMING ERROR:
0 – No framing errors encountered in the receipt of this data.
1 – Framing error occurred. A preamble was followed by something other than another
preamble or start flag, request interrupt.
4 RFS
RECEIVE FIFO SERVICE REQUEST (read-only):
0 – Receive FIFO has not reached it trigger level or receiver disabled.
1 – Receive FIFO has reached its trigger level and receiver is enabled. DMA service
request signalled. Interrupt request signalled if not masked by ICCR0[RIE].
3 TFS
TRANSMIT FIFO SERVICE REQUEST (read-only):
0 – Transmit FIFO has more than 96 entries of data or transmitter disabled.
1 – Transmit FIFO has 96 or less entries of data and transmitter is enabled. DMA service
request signalled. Interrupt request signalled if not masked by ICCR0[TIE].
2 RAB
RECEIVER ABORT:
0 – No abort has been detected for the incoming frame.
1 – Abort detected during receipt of incoming frame. Two or more chips containing no
pulses or any invalid chips were detected on the receive pin. EOF bit set on last
piece of “good” data received before the abort, interrupt requested.
1 TUR
TRANSMIT FIFO UNDERRUN:
0 – Transmit FIFO has not experienced an underrun.
1 – Transmit logic attempted to fetch data from transmit FIFO while it was empty.
Interrupt request signalled if not masked by ICCR0[TUS].
Underruns are not generated when the FICP transmitter is first enabled and is idle.
0 EIF
END/ERROR IN FIFO (read-only).
0 – Bits 8–10 are not set within any of the entries at or below the trigger level of the
receive FIFO. Receive FIFO DMA service requests are enabled.
1 – One or more tag bits (8 – 10) are set within the entries at or below the trigger level of
the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
This interrupt is not maskable in the FICP. Once the bad bytes have been removed from
the FIFO and EIF is cleared, DMA requests are automatically enabled.