Table 9-5. master transactions (sheet 1 of 2) – Intel PXA26X User Manual
Page 350
9-12
Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Bus Interface Unit
Table 9-5. Master Transactions (Sheet 1 of 2)
I
2
C Master
Action
Mode of
Operation
Definition
Generate clock
output
Master-transmit
Master-receive
Master drives the SCL line.
ICR[SCLE] bit must be set.
ICR[IUE] bit must be set.
Write target
slave address
to IDBR
Master-transmit
Master-receive
CPU
writes to IDBR bits 7-1 before a START condition enabled.
First seven bits sent on bus after START.
Section 9.3.3, “Start and Stop Bus States”
Write R/nW Bit
to IDBR
Master-transmit
Master-receive
CPU writes to least significant IDBR bit with target slave address.
If low, master remains a master-transmitter. If high, master transitions to
a master-receiver.
Section 9.4.2, “Data and Addressing Management”
.
Signal START
Condition
Master-transmit
Master-receive
See “Generate clock output” above.
Performed after target slave address and R/nW bit are in IDBR.
Software sets ICR[START] bit.
Software sets ICR[TB] bit to initiate start condition.
Section 9.3.3, “Start and Stop Bus States”
Initiate first
data byte
transfer
Master-transmit
Master-receive
CPU writes byte to IDBR
I
2
C unit transmits byte when ICR[TB] bit is set.
I
2
C unit clears ICR[TB] bit and sets ISR[ITE] bit when transfer is
complete.
Arbitrate for
I
2
C Bus
Master-transmit
Master-receive
If two or more masters signal a start within the same clock period,
arbitration must occur.
I
2
C unit arbitrates for as long as needed. Arbitration takes place during
slave address and R/nW bit or data transmission and continues until all
but one master loses the bus. No data lost.
If I
2
C unit loses arbitration, it sets ISR[ALD] bit after byte transfer is
completed and transitions to slave-receive mode.
If I
2
C unit loses arbitration as it attempts to send target address byte, I
2
C
unit attempts to resend it when the bus becomes free.
System designer must ensure boundary conditions described in
Section 9.4, “Inter-Integrated Circuit Bus Operation”
do not occur.
Write one data
byte to the
IDBR
Master-transmit
only
I
2
C master operation data transmit mode.
Occurs when the ISR[ITE] bit is set and the ICR[TB] bit is clear. If the
IDBR Transmit Empty Interrupt is enabled, it is signalled to the
processor.
CPU writes one data byte to the IDBR, sets the appropriate START/
STOP bit combination, and sets the ICR[TB] bit to send the data. Eight
bits are taken from the shift register and written to the serial bus. The
eight bits are followed by a STOP, if requested.
Wait for
Acknowledge
from slave-
receiver
Master-transmit
only
As a master-transmitter, the I
2
C unit generates the clock for the
acknowledge pulse. The I
2
C unit releases the SDA line to allow slave-
receiver ACK transmission.