Intel PXA26X - Manual (Page 175)

Intel® PXA26x Processor Family Developer’s Manual 5-17
Direct Memory Access Controller
• DCMD[INCSRCADDR] = 1
• DCMD[INCTRGADDR] = 1
• DCMD[FLOWSRC] = 0
• DCMD[FLOWTRG] = 0
• DCSR[RUN] =1
5.3 Direct Memory Access Controller Registers
The section describes the Direct Memory Access Controller registers.
5.3.1 DMA Interrupt Register
The read-only DMA Interrupt Register (DINT) ( Figure 5-6 ) logs the interrupts for each channel.
An interrupt is generated if any of the following events occur:
• Any kind of transaction error on the internal bus that is associated with the relevant channel.
• The current transfer finishes successfully and the DCMD:ENDIRQEN bit is set to a 1.
• The current descriptor loads successfully and the DCMD:STARTIRQEN bit is set to a 1.
• The DCSR:STOPIRQEN is set to a 1 and the relevant channel is in the uninitialized or stopped
state.
Software must write a 1 to the corresponding DCSR register error bit to reset the interrupt.
5.3.2 DMA Channel Control/Status Register
The read/write DMA Channel Control/Status Register (DCSRx) ( Figure 5-7 ) contains the control
and status bit for each channel. Read this register to find the source of an interrupt. Write the read
value back to the register to clear the interrupt.
Table 5-6. DINT Register Bitmap and Bit Definitions
Physical Address
0x4000_00F0
DMA Interrupt Register (DINT) DMA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
C
h
lIntr
15
C
h
lIntr
14
C
h
lIntr
13
C
h
lIntr
12
C
h
lIntr
1
1
C
h
lIntr
10
C
h
lIntr
9
C
h
lIntr
8
C
h
lIntr
7
C
h
lIntr
6
C
h
lIntr
5
C
h
lIntr
4
C
h
lIntr
3
C
h
lIntr
2
C
h
lIntr
1
C
h
lIntr
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:16 — Reserved – Read as unknown and must be written as zero.
15:0 CHLINTRx
CHANNEL ‘X’ INTERRUPT (read-only):
0 – no interrupt
1 – interrupt