Intel PXA26X - Manual (Page 599)

Intel® PXA26x Processor Family Developer’s Manual 17-15
Hardware UART
Table 17-7. Interrupt Conditions
Priority Level Interrupt origin
1 (highest) Receiver line status – one or more error bits were set.
2
Received data is available – In FIFO mode, trigger threshold was reached. In non-FIFO mode,
RBR has data.
2
Receiver timeout occurred – Occurs only in FIFO mode, when data is in the receive FIFO but
no data has been sent for a set time period.
3
Transmitter requests data – In FIFO mode, the transmit FIFO is at least half empty. In non-FIFO
mode, the THR has been transmitted.
4 (lowest) Modem Status – one or more modem input signal has changed state.
Table 17-8. IIR Bit Definitions (Sheet 1 of 2)
Physical Address
0x4160_0008
Interrupt Identification Reg. (IIR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FI
FO
ES
R
eser
ved
AB
L
TO
D
IID nIP
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 1
Bits Access Name Description
31:8 N/A — Reserved – Read as unknown and must be written as zero.
7:6 R FIFOES[1:0]
FIFO MODE ENABLE STATUS:
00 – Non-FIFO mode is selected
01 – Reserved
10 – Reserved
11 – FIFO mode is selected (TRFIFOE = 1)
5 N/A — Reserved – Read as unknown and must be written as zero.
4 R ABL
AUTOBAUD LOCK ( Section 17.4.4, “Auto-Baud-Rate Detection” ):
0 – Autobaud circuitry has not programmed Divisor Latch registers (DLR).
1 – Divisor Latch registers (DLR) programmed by auto-baud circuitry.