Table 10-8. interrupt conditions – Intel PXA26X User Manual
Page 377
Intel® PXA26x Processor Family Developer’s Manual
10-11
Universal Asynchronous Receiver/Transmitter
Table 10-8. Interrupt Conditions
Priority Level
Interrupt origin
1 (highest)
Receiver Line Status – One or more error bits were set
2
Received Data is available – In FIFO mode, trigger level was reached. In
non-FIFO mode, RBR has data.
2
Character Timeout Indication occurred – Occurs only in FIFO mode, when
data is in the receive FIFO but no data has been sent for a set time period.
3
Transmitter requests data – In FIFO mode, the transmit FIFO is at least
half empty. In non-FIFO mode, the THR has been transmitted.
4 (lowest)
Modem Status – one or more modem input signal has changed state.
Table 10-9. Interrupt Identification Register
–
IIR
Base+0x8
Interrupt Identification Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
FIFO
ES
1
FIFO
ES
0
R
eser
ved
R
eser
ved
IID
3
IID
2
IID
1
IP
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Read only
Bits
Name
Description
31:8
—
Reserved
7:6
FIFOES[1:0]
FIFO MODE ENABLE STATUS:
00 – Non-FIFO mode is selected
01 – Reserved
10 – Reserved
11 – FIFO mode is selected (FCR[TRFIFOE] = 1)
5:4
—
Reserved
3
TOD
(IID3)
CHARACTER TIMEOUT INDICATION DETECTED:
0 – No Character Timeout Indication interrupt is pending
1 – Character Timeout Indication interrupt is pending (FIFO mode only)
2:1
IID[2:1]
INTERRUPT SOURCE ENCODED:
00 – Modem Status (CTS, DSR, RI, DCD modem signals changed state)
01 – Transmit FIFO request data
10 – Received Data Available
11 – Receive error (Overrun, parity, framing, break, FIFO error)
0
IP
INTERRUPT PENDING:
0 – Interrupt is pending (Active low)
1 – No interrupt is pending