Intel PXA26X User Manual

Page 90

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3-24

Intel® PXA26x Processor Family Developer’s Manual

Clocks and Power Manager

3.5.2

Power Manager General Configuration Register (PCFR)

Use the PCFR, refer to

Table 3-8

, to configure power manager functions in the processor. When the

OPDE bit is set, it allows the 3.6864-MHz oscillator to be disabled during sleep mode. The OPDE
bit is cleared in hardware, watchdog, and GPIO resets. The Float PCMCIA (FP) and Float Static
Memory (FS) bits control the state of the PCMCIA control pins and the static memory control pins
during sleep mode.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-8. PCFR Bit Definitions

0x40F0_001C

PCFR

Clocks and Power Manager

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Reserved

FS

FP

OP

D

E

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

[31:3]

Reserved

2

FS

Float Static Chip Selects during sleep mode.

0 – Static chip select pins are not floated in sleep mode. nCS[5:1] are driven to the state

of the appropriate PGSR register bits. nCS[0], nWE, and nOE are driven high.

1 – Static chip select pins are floated in sleep mode. The pins nCS[5:0], nWE, and nOE

are affected.

Cleared on hardware, watchdog, and GPIO resets.

1

FP

Float PCMCIA controls during sleep mode.

0 – PCMCIA pins are not floated in sleep mode. They are driven to the state of the

appropriate PGSR register bits.

1 – The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in

sleep mode. nPSKTSEL and nPREG are derived from address signals and assume
the state of the address bus during sleep mode.

Cleared on hardware, watchdog, and GPIO resets.

0

OPDE

3.6864 MHz oscillator power-down enable.

If the 32.7686-KHz crystal is disabled because the OON bit in the Oscillator
Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
disabled.

0 – Do not stop the oscillator during sleep mode.

1 – Stop the 3.6864 MHz oscillator during sleep mode.

Cleared on hardware, watchdog, and GPIO resets.

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