1 servicing internal peripherals – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
Direct Memory Access Controller
5.2.1
Servicing Internal Peripherals
The DMAC provides the DMA Request to Channel Map Registers (DRCMRx) that contain four
bits used to assign a channel number for each possible DMA request. An internal peripheral can be
mapped to any of the 16 available channels. See
Table 5-5, “DMA Quick Reference for Internal
to configure the internal peripherals for DMA accesses. Internal
peripherals assert the request bit through the peripheral request bus (PREQ). The signals from the
PREQ are sampled on every peripheral clock (PCLK) and if any of the PREQ signals are not
zeroes, a lookup is performed on the corresponding bits of the DRCMRx. This allows the request
to be mapped to one of the channels.
If the internal peripheral address is in the DSADR, the DCMDx[FLOWSRC] bit must be set to a 1.
This allows the processor to wait for the request before it initiates the transfer. If the internal
peripheral address is in the DTADR, the DCMDx[FLOWTRG] bit must be set to a 1.
If DCMDx[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle
associated with the byte that caused DCMDx[LENGTH] to decrement to 0.
5.2.1.1
Using Flow-Through DMA Read Cycles to Service Internal
Peripherals
A flow-through DMA read for an internal peripheral begins when the internal peripheral sends a
request, via the PREQ bus, to a DMAC channel that is running and configured for a flow-through
read. The number of bytes to be transferred is specified with DCMDx[SIZE]. When the request is
the highest priority request, the following process begins:
1. The DMAC sends the memory controller a request to read the number of bytes addressed by
DSADRx[31:0] into a 32-byte staging buffer in the DMAC.
2. The DMAC transfers the data to the I/O device addressed in DTADRx[31:0].
DCMD[WIDTH] specifies the width of the internal peripheral to which the data is transferred.
3. At the end of the transfer, DSADRx is increased by the smaller value of DCMDx[LENGTH]
and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same value.
For a flow-through DMA read to an internal peripheral, use the following settings for the DMAC
register bits:
•
DSADR[SRCADDR] = external memory address
•
DTADR[TRGADDR] = internal peripheral’s address
•
DCMD[INCSRCADDR] = 1
•
DCMD[FLOWSRC] = 0
•
DCMD[FLOWTRG] = 1
5.2.1.2
Using Flow-Through DMA Write Cycles to Service Internal
Peripherals
A flow-through DMA write for an internal peripheral begins when the internal peripheral sends a
request, via the PREQ bus, to a DMAC channel that is running and configured for a flow-through
write. The number of bytes to be transferred are specified with DCMDx[SIZE]. When the request
is the highest priority request, the following process begins: