Intel PXA26X - Manual (Page 70)

3-4 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
3.3.1 32.768-KHz Oscillator
The 32.768-KHz oscillator is a low-power, low-frequency oscillator that clocks the RTC and power
manager. The 32.768-KHz oscillator is disabled out of hardware reset so the RTC and power
manager blocks use the 3.6864-MHz oscillator instead. Software writes the Oscillator On bit in the
Oscillator Configuration Register to enable the 32.768-KHz oscillator. This configures the RTC
and power manager to use the 32.768-KHz oscillator after it stabilizes.
32.768-KHz oscillator use is optional and provides the lowest power consumption during sleep
mode. In less power-sensitive applications, disable the 32.768-KHz oscillator in the Oscillator
Configuration Register (OSCC) and leave the external pins floating (no external crystal required)
for cost savings. If the 32.768-KHz oscillator is not in the system, the frequency of the RTC and
power manager will be 3.6864 MHz divided by 112 (32.914 KHz). In sleep, the 3.6864-MHz
oscillator consumes hundreds of microamps of extra power when it stays enabled. See
Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for
information on the Oscillator Power Down Enable (OPDE) bit, which determines if the 3.6864-
MHz oscillator is enabled in sleep mode. No external capacitors are required.
3.3.2 3.6864-MHz Oscillator
The 3.6864-MHz oscillator provides the primary clock source for the processor. The on-chip PLL
frequency multipliers, Synchronous Serial Port (SSP), Pulse Width Modulator (PWM), and the
Operating System Timer (OST) use the 3.6864-MHz oscillator as a reference. Out of hardware
reset, the 3.6864-MHz oscillator also drives the RTC and power manager (PM). The user may then
enable the 32.768-KHz oscillator, which drives the RTC and PM after it is stabilized. The 3.6864-
MHz oscillator can be disabled during sleep mode by setting the OPDE bit (see
Section 3.5.2,
“Power Manager General Configuration Register (PCFR)” on page 3-24 ) but only if the 32.768-
KHz oscillator is enabled and stabilized (both the OON and OOK bits in the OSCC set). See
Section 3.6.3, “Oscillator Configuration Register (OSCC)” on page 3-39 for more information. No
external capacitors are required.
3.3.3 Core Phase Locked Loop
The core PLL is the clock source of the CPU core, the memory controller, the LCD controller, and
DMA controller. The core PLL uses the 3.6864-MHz oscillator as a reference and multiplies its
frequency by the following variables:
• L: crystal frequency to memory frequency multiplier, set to 27, 32, 36, 40, or 45.
• M: memory frequency to run mode frequency multiplier, set to 1, 2 or 4.
• N: run mode frequency to turbo mode frequency multiplier, set to 1.0, 1.5, 2.0, or 3.0.
The output frequency selections are shown in Table 3-1, on page 3-5 . See Section 3.6.1, “Core
Clock Configuration Register (CCCR)” on page 3-35 for programming information on the L, M,
and N factors. See Section 3.6.1 for the hexadecimal settings.
Do not choose a combination that generates a frequency that is not supported in the voltage range
and package in which the processor is operating.
SDCLK must not be greater than 100 MHz for SDRAM and 66 MHz for internal Flash. If
MEMCLK is greater than 100 MHz, the SDCLK to MEMCLK ratio must be set to 1:2 in the
memory controller.