Intel PXA26X - Manual (Page 73)

Intel® PXA26x Processor Family Developer’s Manual 3-7
Clocks and Power Manager
3.4.1 Hardware Reset
To invoke a hardware reset and reset all units in the processor to a known state, assert the nRESET
pin. Hardware reset is only intended to be used for power up and complete resets.
3.4.1.1 Invoking Hardware Reset
Hardware reset is invoked when the nRESET pin is pulled low by an external source. The
processor does not provide a method of masking or disabling the propagation of the external pin
value. When the nRESET pin is asserted, a hardware reset is invoked, regardless of the mode of
operation. The nRESET_OUT pin is asserted when the nRESET pin is asserted. To enter hardware
reset, nRESET must be held low for t
DHW_NRESET
to allow the system to stabilize and the reset
state to propagate. Refer to the Intel® PXA26x Processor Family Electrical, Mechanical, and
Thermal Specification for details.
3.4.1.2 Behavior During Hardware Reset
During hardware reset, all internal registers and units are held at their defined reset conditions.
While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864-MHz
oscillator. The internal clocks are stopped and the chip is static. All pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory
controller receives a full reset, all dynamic RAM contents are lost during hardware reset.
3.4.1.3 Completing Hardware Reset
To complete a hardware reset, deassert the nRESET pin. All power supplies must be stable for
t
D_NRESET
before nRESET is deasserted. Refer to the Intel® PXA26x Processor Family Electrical,
Mechanical, and Thermal Specification for details. After the nRESET pin is deasserted, this
sequence occurs:
1. The 3.6864-MHz oscillator and internal PLL clock generators wait for stabilization.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units return to their predefined reset
conditions. Software must examine the Reset Controller Status Register (RCSR) to determine
the cause for the boot.
3.4.2 Watchdog Reset
Watchdog reset is invoked when software fails to properly prevent the watchdog time-out event
from occurring. It is assumed that watchdog resets are only generated when software is not
executing properly and has potentially destroyed data. In watchdog reset, all units in the processor
are reset except the clocks and power manager.
3.4.2.1 Invoking Watchdog Reset
Watchdog reset is invoked when the Watchdog Enable (WE) bit in the OS Timer Watchdog Match
Enable Register (OWER) is set and the OS Timer Match Register 3 (OSMR3) matches the OS
timer counter. When these conditions are met, they invoke watchdog reset, regardless of the
previous mode of operation. Watchdog reset asserts nRESET_OUT.