Intel PXA26X - Manual (Page 293)

Intel® PXA26x Processor Family Developer’s Manual 7-25
Liquid Crystal Display Controller
7.6.1.8 End of Frame Mask (EFM)
The end of frame mask (EFM) bit masks interrupt requests that are asserted at the end of each
frame (when the DMA length of transfer counter decrements to zero). When EFM=0, the interrupt
is enabled, and whenever the EOF status bit in the LCD status register (LCSR) is set to one, an
interrupt request is made to the interrupt controller. When EFM=1, the interrupt is masked, and the
state of the EOF status bit is ignored by the interrupt controller. Setting EFM does not affect the
current state of EOF or the LCD controller’s ability to set and clear EOF, it only blocks the
generation of the interrupt request.
7.6.1.9 Input Fifo Underrun Mask (IUM)
The input FIFO underrun mask (IUM) bit masks interrupt requests that are asserted whenever an
input FIFO underrun error occurs. When IUM=0, underrun interrupts are enabled, and whenever an
input FIFO underrun (IUL, IUU) status bit in the LCD status register (LCSR) is set to one, an
interrupt request is made to the interrupt controller. When IUM=1, underrun interrupts are masked
and the state of the underrun status bits (IUL, IUU) is ignored by the interrupt controller. Setting
IUM does not affect the current state of these status bits or the LCD controller’s ability to set and
clear them, it only blocks the generation of the interrupt requests.
7.6.1.10 Start Of Frame Mask (SFM)
The start of frame interrupt mask (SFM) bit masks interrupt requests that are asserted at the
beginning of each frame when the LCD’s frame descriptor has been loaded into the internal DMA
registers. When SFM=0, the interrupt is enabled, and whenever the LCSR[SOF] status bit is set, an
interrupt request is made to the interrupt controller. When SFM=1, the interrupt is masked and the
state of the SOF status bit is ignored by the interrupt controller. Setting SFM does not affect the
current state of SOF or the LCD controller’s ability to set and clear SOF, it only blocks the
generation of the interrupt request.
7.6.1.11 LCD Disable Done Interrupt Mask (LDM)
The LCD disable done interrupt mask (LDM) bit masks interrupt requests that are asserted after the
LCD is disabled and the frame currently being sent to the output pins has completed. When
LDM=0, the interrupt is not masked, and whenever the LCSR[LDD] status bit is set to one, an
interrupt request is made to the interrupt controller. When LDM=1, the interrupt is masked, and the
state of the LDD status bit is ignored by the interrupt controller. Setting LDM does not affect the
current state of LDD or the LCD controller’s ability to set and clear LDD, it only blocks the
generation of the interrupt request. This interrupt is used when the LCD must be disabled after the
current frame being sent to the output pins has completed. Clearing LCD enable (ENB) is a quick
disable, and LDD is not set.
Note: This mask bit applies only to regular shutdowns using the LCD disable (DIS) bit.
Figure 7-17. Frame Buffer/Palette Output to LCD Data Pins in Active Mode
4/8/16 Bits/Pixel Mode, Frame Buffer or Palette Entry
PIxel R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L_DD
Pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0