Intel PXA26X - Manual (Page 274)

7-6 Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
• Section 7.3.3, “Temporal Modulated Energy Distribution (TMED) Dithering”
• Section 7.3.4, “Output FIFOs”
• Section 7.3.5, “Liquid Crystal Display Controller Pin Usage”
• Section 7.3.6, “Direct Memory Access”
7.3.1 Input FIFOs
Data fetched from external memory by the dedicated DMAC is placed in one of two input FIFO
buffers. Each input FIFO comprises 128 bytes, organized as 16 entries by 8 bytes. In single-panel
mode, one FIFO queues both encoded pixel data and data for writing to the internal palette RAM.
In dual-panel mode, this FIFO queues data for the internal palette RAM and the upper half of the
LCD display, while the second FIFO buffer holds data for the lower half of the LCD display.
The FIFO signals a service request to the DMAC whenever four FIFO entries are empty. In turn,
the DMAC automatically fills the FIFO with a 32-byte burst. Pixel data from the frame buffer
remains packed within individual 8-byte entries when it is loaded into the FIFO. If the pixel size is
1-, 2-, 4-, or 8-bits, the FIFO entries are unpacked and used to index the palette RAM to read the
color value. In 16-bit passive mode, the entries bypass the palette and go directly to the TMED
dither logic. In 16-bit active mode, the pixels are sent directly to the pins.
7.3.2 Lookup Palette
The internal palette RAM holds up to 256 16-bit color values. Color palette RAM entries are 16-
bits wide, with 5 bits of red, 6 bits of green, and 5 bits of blue. Pixel-encoding-bit size is:
• Monochrome entries are 8-bits wide
• Encoded pixel values from the input FIFO are used as an address to index and select individual
palette locations:
— 1-bit-pixel encodings address the first 2 entries
— 2-bit-pixel encodings address the first 4 entries
— 4-bit-pixel encodings address 16 locations
— 8-bit-pixel encodings select any of the 256 palette entries.
• In 16-bit pixel mode, the palette RAM is not used and must not be loaded.
7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering
For passive displays, entries selected from the lookup palette (or directly from memory for 16-bit
pixels) are sent to the TMED dithering algorithm. TMED is a form of temporal dithering, also
know as frame rate control. The algorithm determines whether a pixel is on or off.
It is not necessary to understand how the TMED dithering algorithm works to use the LCD
controller. However, certain characteristics of the algorithm can be controlled through the use of
the TMEDRGB Seed Register (TRGBR) (refer to
Table 7-14 ) and the TMED Control Register
(TCR) (refer to Table 7-15 ). If these registers are to be modified from their default values, refer to
this section. Figure 7-2 illustrates the TMED concept.