Intel PXA26X - Manual (Page 139)

Intel® PXA26x Processor Family Developer’s Manual 4-31
System Integration Unit
Several units have more than one source per interrupt signal. When an interrupt is signalled from
one of these units, the interrupt handler routine identifies which interrupt was signalled using the
interrupt controller’s pending register. This identifies the unit that made the request, but not the
exact source. The handler then reads the interrupting unit’s status register to identify which source
within the unit signalled the interrupt. For all interrupts that have one corresponding source, the
interrupt handler routine needs to use only the interrupt controller’s registers to identify the exact
cause of the interrupt. ICPR(6:0) are reserved bits and must be written as zeros. Reads to these bits
must be ignored.
4.2.3 Interrupt Controller Register Locations
Table 4-38 shows the registers associated with the interrupt controller block and their physical
addresses.
IS<10> 88 “OR” of GPIO edge detects 90-2
IS<9> 1 GPIO<1> edge detect
IS<8> 1 GPIO<0> edge detect
IS<7> Hardware UART 7 Hardware UART service request
IS<6> Reserved
IS<5> Reserved
IS<4> Reserved
IS<3> Reserved
IS<2> Reserved
IS<1> Reserved
IS<0> Reserved
Total level 2 interrupt
sources
203
Table 4-37. List of First–Level Interrupts (Sheet 2 of 2)
Bit Position Source Unit # of Level 2 Sources Bit Field Description
Table 4-38. Interrupt Controller Register Addresses
Address Name Description
0x40D0_0000 ICIP Interrupt controller IRQ pending register
0x40D0_0004 ICMR Interrupt controller mask register
0x40D0_0008 ICLR Interrupt controller level register
0x40D0_000C ICFP Interrupt controller FIQ pending register
0x40D0_0010 ICPR Interrupt controller pending register
0x40D0_0014 ICCR Interrupt controller control register