Intel PXA26X - Manual (Page 152)

4-44 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
4.5.1.1 Interdependencies
The PWM unit is clocked off the 3.6864-MHz oscillator output.
Each Pulse Width Modulator Unit (PWMn) is controlled by three registers:
• Pulse Width Control Register (PWM_CTRL)
• Duty Cycle Control Register (PWM_DUTY)
• Period Control Register (PWM_PERVAL)
By setting the values in these registers the PWMn unit produces a pulse width modulated output
signal. The registers contain the values for PWMn’s counters and PWMn power management
mode.
Each register contains one or more fields which determine an attribute of the PWM_OUTn
waveform. PWM_CTRLn[PRESCALE] specifies the divisor for the PWM module clock. Note
that the actual PWM module clock divisor used is 1 greater than the value programmed into
PWM_CTRLn[PRESCALE]. This divided PWM module clock drives a 10 bit up-counter. This up-
counter feeds 2 separate comparators. The first comparator contains the value of
PWM_DUTYn[DCYCLE]. When the values match, the PWM_OUT signal is set high. The other
comparator contains PWM_PERVALn[PV] and clears the PWM_OUT signal low when
PWM_PERVALn[PV] + 1 and the 10-bit up counter are equal. Both PWM_PERVALn[PV] and
PWM_DUTYn[DCYCLE] are 10 bit fields.
Note: Take care to ensure that the value of the PWM_PERVALn register remains larger than
PWM_DUTYn register. In the case where PWM_PERVALn is less than PWM_DUTYn the output
maintains a high state.
4.5.1.2 Reset Sequence
A system reset results in no pulse width modulated signal. During system reset the PWM_CTRLn
and PWM_DUTYn registers are reset to 0x0 and the PWM_PERVALn register is set to 0x004.
This sets the PWM_OUTn pin low with a zero duty cycle. The six bit down-counter is reset to 0x0
and thus the 3.68-MHz-input clock directly drives the 10 bit up-counter. The PWM_OUTn pin
remains reset low until the PWM_DUTYn register is programmed with a non zero value.
A basic pulse width waveform is shown in Figure 4-4 on page 4-47 .
4.5.1.3 Power Management Requirements
Each PWM may be disabled through a pair of clock enable bits (see Section 3.6.2, “Clock Enable
Register (CKEN)” on page 3-37 ). If the clock is disabled, the unit shuts down in one of two ways:
• Abrupt – the PWM stops immediately.
• Graceful – the PWM completes the current duty cycle before stopping.
Shutdown is selected by PWM_CTRL[PWM_SD] and described in Section 4.5.2.1, “PWM
Control Registers (PWM_CTRLn)” on page 4-45 .
4.5.2 Register Descriptions
The following paragraphs provide register descriptions for the Pulse Width Modulator.