2 power mode register (pwrmode), 8 external hardware considerations, 1 power-on-reset considerations – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
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Clocks and Power Manager
3.7.2
Power Mode Register (PWRMODE)
Use the PWRMODE register (CP14, register 7), refer to
Table 3-27
, to enter idle and sleep modes.
To select a mode, software writes to PWRMODE[M]. All core-initiated memory requests are
completed before the clocks and power manager initiates the desired mode.
3.8
External Hardware Considerations
The clocks and power manager controls the timing in and out of resets and the voltage ramp and
stabilization. As a result, the hardware used with the processor must meet certain requirements to
operate properly. This section describes those requirements.
3.8.1
Power-On-Reset Considerations
The nRESET and nTRST pins must be held low while the power supplies initialize and for a fixed
time after power is stable. This can be controlled with an external power-on-reset device or another
circuit.
To ensure that the internal ESD protection devices do not activate during power up, a minimum rise
time must be observed. Refer to the Intel® PXA26x Processor Family Electrical, Mechanical, and
Thermal Specification for details.
3.8.2
Driving the Crystal Pins from an External Clock Source
The information in this section is provided as a guideline. The electrical specifications for the
crystal oscillator pins are in Intel® PXA26x Processor Family Electrical, Mechanical, and
Thermal Specification.
Table 3-27. PWRMODE Bit Definitions
CP14
Register 7
PWRMODE
CP14
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
M
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[31:2]
—
Reserved
[1:0]
M
LOW POWER MODE:
00 – Run/turbo mode
01 – Idle mode
10 – Reserved
11 – Sleep mode
Set to 00 on reset.