Intel PXA26X - Manual (Page 470)

13-8 Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
13.4.1.6 Slot 5: Modem Line Codec
Audio output frame slot 5 contains the MSB justified modem DAC input data if the line codec is
supported. The optional modem DAC input resolution can be implemented as 16, 18, or 20 bits. If
the modem line codec is supported, the ACUNIT driver determines the DAC resolution at boot
time. During normal runtime operation, the ACUNIT fills all trailing non-valid bit positions in the
slot with zeroes. The modem codec may be a separate codec on the secondary line or integrated
with the audio codec.
13.4.1.7 Slots 6-11: Reserved
These audio output frame slots are reserved for future use and the ACUNIT fills them with zeroes.
13.4.1.8 Slot 12: I/O Control
Slot 12 has 16 MSB bits for GPIO Control (output) and Status (input). The bits are used to
minimize access latency that results from changing conditions. The bits’ values are the values
written to the Codec GPIO Status Register at address 0x54 in the modem codec I/O space. The
following rules govern slot 12 use:
1. Slot 12 is initially marked invalid by default.
2. A write to address 0x54 in codec I/O space transfers the data out of slot 12 in the next frame
and slot 12 is marked valid. The data is also sent out on slots 1 and 2.
3. After the first write to address 0x54, slot 12 remains valid for all subsequent frames. The data
transmitted on slot 12 is the data last written to address 0x54. Any subsequent write to the
register sends the new data out on the next frame.
4. Following a system reset or AC97 cold reset, slot 12 is invalidated. Slot 12 remains invalid
until the next write to the address 0x54.
13.4.2 AC-link Audio Input Frame (SDATA_IN)
The ACUNIT has two SDATA_IN lines, a primary and a secondary. Each line can have codecs
attached. The type of codec attached determines which slots are valid or invalid. The data slots on
the two inputs are completely orthogonal (i.e., no two data slots at the same location will be valid
on both lines).
Multiple input data streams are received and multiplexed on slot boundaries as dictated by the slot
valid bits in each stream. Each AC-link audio input frame consists of twelve 20-bit time slots. Slot
0 is reserved and contains 16 bits that are used for AC-link protocol infrastructure.
Software must poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication
that the controller is in the codec ready state before it places the ACUNIT into operation. When the
controller is sampled codec ready, the next 12 bit positions sampled indicate which of the 12 time
slots are assigned to input data streams and whether they contain valid data.
Figure 13-5, “AC97
Input Frame” illustrates the time slot-based AC-link protocol.