Intel PXA26X - Manual (Page 144)

4-36 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
4.3.3.1 Oscillator Frequency Calibration
To determine the value programmed into the RTTR, you must first measure the output frequency at
the oscillator multiplexor (approximately 32 KHz) using an accurate time base, such as a frequency
counter. This clock is externally visible by selecting the alternate function for GPIO[12] or
GPIO[72]. To gain access to the clock, program this pin as an output and then switch to the
alternate function. Refer to
Section 4.1 on page 4-1 , for details on how to make the clock externally
visible. To trim the clock, divide the output of the oscillator by an integer value and fractional
adjust it by periodically deleting clocks from the stream driving this integer divider.
4.3.3.2 RTTR Value Calculations
After the true frequency of the oscillator is known, it must be divided by the desired Hz clock
frequency and this value split into integer and fractional portions. The integer portion of the value
(minus one) is loaded into the Clock Divider Count field of the RTTR. This value is compared
against a 16-bit counter clocked by the output of the oscillator multiplexor at approximately
32 KHz. When the two values are equal, the counter resets and generates a pulse which constitutes
the raw Hz-clock signal.
The fractional part of the adjustment is done by periodically deleting clocks from the clock stream
driving the integer counter. The trim interval period is hardwired to be 2
10
-1 periods of the Hz
clock. If the Hz clock is programed to be 1 Hz the trim interval would be approximately 17
minutes. The number of clocks deleted (the trim delete value) is a 10-bit programmable counter
allowing from 0 to 2
10
-1 32-KHz clocks to be deleted from the input clock stream once per trim
interval. RTTR[25:16] represents the number of 32-KHz clocks deleted per trim operation.
In summary, every 2
10
-1 Hz clock periods, the integer counter stops clocking for a period equal to
the fractional error that has accumulated. If this fractional error is programmed to be zero, then no
trim operations occur and the RTC is clocked with the raw 32-KHz clock. The relationship between
the Hz clock frequency and the nominal 32-KHz clock (f1 and f32K, respectively) is shown in the
following equation.
f1 = Hz clock frequency
f32k = RTC internal clock - either the 32.678-KHz crystal output or the 3.68-MHz crystal
output divided down to 32.914 KHz
RTTR[DEL] = RTTR(25:16)
RTTR[CK_DIV] = RTTR(15:0)
4.3.3.2.1 Trim Example #1 – Measured Value Has No Fractional Component
In this example, the desired Hz clock frequency is 1 Hz. The oscillator output is measured as
36045.000 cycles/s (Hz). This output is exactly 3277 cycles over the nominal frequency of the
crystal (32.768 KHz) and has no fractional component. As such, only the integer trim function is
needed - no fractional trim is required. Accordingly, RTTR[15:0] is loaded with the binary
equivalent of 36045-1, or 0x0000_8CCC. RTTR[25:16] is left at zero (power-up state) to disable
fractional trimming. This trim exercise leaves an error of zero in trimming.
f1 =
(2^10-1)*(RTTR[CK_DIV]+1) - RTTR[DEL]
(2^10-1)*(RTTR[CK_DIV]+1)
*
f32k
(RTTR[CK_DIV]+1)