Intel PXA26X User Manual
Page 97
Intel® PXA26x Processor Family Developer’s Manual
3-31
Clocks and Power Manager
3.5.9
Power Manager Fast Sleep Wake Up Configuration Register
(PMFWR)
The power manager contains a 32-bit register that configures the processor sleep-wake-up
sequence. The PMFWR, refer to
Table 3-15
, contains a single configurable bit: FWAKE. Use the
PMFWR[FWAKE] bit to select between the standard and fast-sleep-wake-up sequences. The
PMFWR register is reset by a hardware reset, but is not cleared by the sleep-wake-up sequence.
Using an exception handler to enter sleep in response to a power-fault event is advantageous
because software can clear the PMFWR[FWAKE] bit and configure the power management IC to
use PWR_EN to disable the core power supply during sleep. Thus minimizing power consumption
from a critically low battery. Also, the PCFR[OPDE] bit must be cleared to enable the 3.6864-MHz
oscillator during sleep when fast-sleep wake up is selected.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
3.5.10
Power Manager GPIO Sleep State Registers (PGSR0,
PGSR1, PGSR2)
PGSR0, PGSR1, and PGSR2, shown in
Table 3-16
,
Table 3-17
, and
Table 3-18
let software select
the output state of each GPIO pin when the processor goes into sleep mode. When a transition to
sleep mode is required (through software or the nBATT_FAULT or nVDD_FAULT pin), the
contents of the PGSR registers are loaded into the GPIO output data registers. Software normally
controls this through GPSR and GPCR. Only pins that are already configured as outputs reflect the
new state. All bits in the output registers are loaded. When the processor re-enters the run mode,
these GPIO pins retain the programmed sleep state until software resets the PSSR[PH] bit. If a pin
is reconfigured from an input to an output, the register’s last contents are driven onto the pin.
Table 3-15. PMFWR Register Bitmap and Bit Definitions
0x40F0 0034
Power Manager Fast Sleep Wake
Up Configuration Register
(PMFWR)
Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Re
s
e
rv
e
d
FW
AKE
Re
s
e
rv
e
d
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[31:3]
—
Reserved.
Read undefined and must always be written with zeroes.
[1]
FWAKE
FAST WAKE UP ENABLE:
0 – Selects the standard-sleep-wake-up sequence with a 10 ms power supply stabili-
zation delay when power is disabled during sleep.
1 – Selects the fast-sleep-wake-up sequence without a power supply stabilization delay
when power is maintained during sleep.
Cleared by hardware reset.
[0]
—
Reserved.
Read undefined and must always be written with zeroes.