Intel PXA26X - Manual (Page 75)

Intel® PXA26x Processor Family Developer’s Manual 3-9
Clocks and Power Manager
GPIO reset does not function in sleep mode because all GPIO pins’ alternate function inputs are
disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up
sources (see
Section 3.5.3, on page 3-25 for details) during sleep mode. GP[1] may be enabled as a
wake-up source.
3.4.3.2 Behavior During GPIO Reset
During GPIO reset, most, but not all, internal registers and processes are held at their defined reset
conditions. The exceptions are the RTC, the clocks and power manager (unless otherwise noted),
and the memory controller. During GPIO reset, the clocks unit continues to operate with its
previously programmed values, so the processor enters and exits GPIO reset with the same clock
configurations. All pins except the oscillator and memory controller pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored.
GPIO reset does not reset the Memory Controller Configuration registers. This creates the
possibility that the contents of external memories may be preserved if the external memories are
properly configured before GPIO reset is entered. To preserve SDRAM contents during a GPIO
reset, software must correctly configure the memory control and the time spent in GPIO reset must
be shorter than the SDRAM refresh interval. The amount of time spent in GPIO reset depends on
the CPU mode before GPIO reset. See
Section 6, “Memory Controller” for details.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Processor Family” on page 2-9 for
the states of all the PXA26x processor family pins during GPIO reset and other resets.
3.4.3.3 Completing GPIO Reset
GPIO reset immediately reverts to hardware reset when the nRESET pin is asserted. Otherwise, the
completion sequence for GPIO reset is:
1. The GPIO reset source is deasserted because the internal reset has propagated to the GPIO
controller and its registers, which are driven to their reset states.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units except the real time clock, parts of
the clocks and power manager, and the memory controller return to their predefined reset
conditions. Software must examine the RCSR to determine the cause for the reset.
3.4.4 Run Mode
Run mode is the processor’s normal operating mode. All power supplies are enabled and all
functionally enabled clocks are running. Run mode is entered after any power mode, power
sequence, or reset completes its sequence. Run mode is exited when any other power mode, power
sequence, or reset begins.
3.4.5 Turbo Mode
Turbo mode allows the user to clock the processor core at a higher frequency during peak
processing requirements. It allows a synchronous switch in frequencies without disrupting the
memory controller, LCD controller, or any peripheral.