Intel PXA26X - Manual (Page 572)

16-24 Intel® PXA26x Processor Family Developer’s Manual
Network/Audio Synchronous Serial Protocol Serial Ports
21 R/W TSRE
TRANSMIT SERVICE REQUEST ENABLE:
Enables the transmit FIFO DMA service request.
NOTE: Clearing TSRE does not affect the current state of SSSR[TFS]
or the ability of the transmit FIFO logic to set and clear
SSSR[TFS]; it blocks only the generation of the DMA Service
Request. The state of TSRE does not effect the generation of
the interrupt, which is asserted whenever the SSSR[TFS] is
set.
0 – DMA service request is disabled and the state of the transmit FIFO
service request is ignored.
1 – DMA service request is enabled.
20 R/W RSRE
RECEIVE SERVICE REQUEST ENABLE:
Enables the receive FIFO DMA Service Request.
NOTE: Clearing RSRE does not affect the current state of SSSR[RFS]
or the ability of the receive FIFO logic to set and clear
SSSR[RFS]; it blocks only the generation of the DMA Service
Request. The state of RFRS does not affect the generation of
the interrupt, which is asserted whenever the SSSR[RFS] is
set.
0 – DMA service request is disabled and the state of the SSSR[RFS] is
ignored.
1 – DMA service request is enabled.
19 R/W TINTE
TIME-OUT INTERRUPT ENABLE:
Enables the receiver time-out interrupt.
NOTE: Clearing TINTE does not affect the current state of the
SSSR[TINT] or the ability of logic to set and clear the
SSSR[TINT]; it blocks only the generation of the Interrupt
request.
0 – Receiver time-out interrupts are disabled. The Interrupt is masked
and the state of SSSR[TINT] is ignored by the Interrupt controller.
1 – Receiver time-out interrupts are enabled.
18:16 — — Reserved
15 R/W STRF
SELECT FIFO FOR EFWR (test mode bit):
Selects whether the transmit or the receive FIFO is enabled for writes
and reads (when the SSP port is in test mode).
0 – Transmit FIFO is selected for both writes and reads through SSDR
1 – Receive FIFO is selected for both writes and reads through SSDR
Table 16-4. SSCR1 Bit Definitions (Sheet 4 of 6)
Physical Address
Base+0x04
SSCR1
PXA26x processor family Network/Audio
SSP Serial Ports
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTELP
TTE
EB
CEI
SC
F
R
Re
s
e
rv
e
d
SC
L
K
D
IR
S
F
RM
DI
R
RW
O
T
Re
s
e
rv
e
d
TS
R
E
RS
R
E
TIN
T
E
Re
s
e
rv
e
d
STRF EFW
R
RFT TFT
MW
D
S
SPH SP
O
LB
M
TIE RI
E
Reset 0 0 0 0 ? ? 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access Name Description