Intel PXA26X - Manual (Page 84)

3-18 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
in software by reading the Saved Program Status Register (SPSR) to see if the previous context
was executing in abort mode.
To enter sleep mode, software must complete this sequence:
1. Software uses external memory and the Power Manager Scratch Pad Register (PSPR) to
preserve critical states.
2. Software sets sleep mode in PWRMODE[M]. An interrupt immediately aborts sleep mode and
normal processing resumes.
3. The CPU waits until all instructions in the pipeline are complete.
4. The memory controller completes outstanding transactions in its buffers and from the CPU.
New transactions from the LCD or DMA controllers are ignored.
5. The memory controller places the SDRAM in self-refresh mode.
6. The power manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the Power Manager GPIO Sleep State registers (PGSR0,
PGSR1, and PGSR2). To avoid contention on the bus when the processor attempts to wake up,
ensure that the chip selects are not set to 0 during sleep mode.
7. The CPU clock stops and power is removed from the Core.
8. PWR_EN is deasserted.
When the power manger gets the indication from the memory controller that it has finished its
outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles
before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT
asserts low.
In some systems the imprecise data abort latency lasts longer than the residual charge in the failed
power supply can sustain operation. This normally only occurs when the processor is in a power
mode or sequence that requires that the processor exit before sleep mode starts. Frequency change
sequence is an example of such a power sequence. In these power modes and sequences, the IDAE
bit must not be set. This allows the processor to enter sleep mode immediately but any critical
states in the processor are lost.
If the IDAE bit is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the sleep
sequence begins at step 4 in the list above.
3.4.9.4 Behavior in Sleep Mode
In sleep mode, all processor and peripheral clocks (except the RTC) are disabled. The processor
does not recognize interrupts or external pin transitions except valid wake-up signals, reset signals,
and the nBATT_FAULT signal.
If the nBATT_FAULT signal is asserted while in sleep mode, GPIO[1:0] are set as the only valid
wake-up signals.
The power manager watches for wake up events programmed by the CPU before sleep mode starts
or set by the power manager it detects a fault condition. In order to detect a GPIO pin rising-edge or
falling-edge, the rising- or falling-edge must be held for more than one full 32.768-KHz-clock
cycle. The power manager takes three 32.768-KHz-clock cycles to acknowledge the GPIO edge
and begin the wake up sequence.