Intel PXA26X - Manual (Page 131)

Intel® PXA26x Processor Family Developer’s Manual 4-23
System Integration Unit
4.2.1 Interrupt Controller Operation
The Interrupt Controller provides masking capability for all interrupt sources and generates either
an FIQ or IRQ processor interrupt. The interrupt hierarchy of the processor is a two-level structure.
• The first level identifies the interrupts from all the enabled and unmasked interrupt sources in
the Interrupt Controller Mask register (ICMR). First level interrupts are controlled by these
registers:
— Interrupt Controller Pending register (ICPR) – identifies all the active interrupts within
the system
— Interrupt Controller IRQ Pending register (ICIP) – contains the interrupts from all sources
that can generate an IRQ interrupt. The Interrupt Controller Level register (ICLR) is
programmed to send interrupts to the ICIP to generate an IRQ.
— Interrupt Controller FIQ Pending register (ICFP) – contains the interrupts from all
sources that can generate an FIQ interrupt. The Interrupt Controller Level register (ICLR)
is programmed to send interrupts to the ICFP to generate an FIQ.
• The second level uses registers contained in the source device (the device generating the first-
level interrupt bit). The second-level interrupt status gives additional information about the
interrupt and is used inside the interrupt service routine. In general, multiple second-level
interrupts are OR’ed to produce a first-level interrupt bit.
In most cases, the root cause of an interrupt can be determined by reading two register locations:
the ICIP for an IRQ interrupt or the ICFP for an FIQ interrupt to determine the interrupting device.
You then read the status register within that device to find the exact function requesting service.
When the ICCR[DIM] bit is zero, the Interrupt Mask Register is ignored during IDLE mode, and
all enabled interrupts cause the processor to exit from idle mode. Otherwise, only unmasked
interrupts cause the processor to exit from idle mode. The reset state of ICCR[DIM] is zero.
Figure 4-2, “Interrupt Controller Block Diagram” on page 4-24 shows a block diagram of the
Interrupt Controller.