Intel PXA26X - Manual (Page 315)

Intel® PXA26x Processor Family Developer’s Manual 7-47
Liquid Crystal Display Controller
(DSTN) displays. The default, recommended setting is 0x00AA5500. This setting provides
superior display results in most cases. This is a write-only register. Write reserved bits with zeros
and ignore reads from reserved bits.
7.6.10 TMED Control Register (TCR)
This read/write register ( Table 7-15 ) selects various options available in the TMED dither
algorithm. There are two available Temporal Modulated Energy Distribution algorithms. The
default setting should be 0x0000754F. This setting provides superior display results in most cases.
Write reserved bits with zeros and ignore reads from reserved bits (refer to
Table 7-15 ).
For more details on the effects of the individual fields within this register, refer to Section 7.3.3,
“Temporal Modulated Energy Distribution (TMED) Dithering” on page 7-6 .
Table 7-14. TMED RGB Seed Register
Physical Address
0x4400_0040
TMED RGB Seed Register LCD Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBS TGS TRS
Reset X X X X X X X X 0xAA 0x55 0x00
Bits Name Description
31:24 — Reserved
23:16 TBS TME BLUE SEED VALUE
15:8 TGS TME GREEN SEED VALUE
7:0 TRS TME RED SEED VALUE
Table 7-15. TMED Control Register (Sheet 1 of 2)
Physical Address
0X4400_0044
TMED Control Register LCD Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TE
D
reser
ved
THBS TVBS
FN
A
M
E
CO
AE
FN
A
M
CO
AM
Reset X X X X X X X X X X X X X X X X X 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1
Bits Name Description
31:15 — Reserved – Must be written with zeros
14 TED
TMED ENERGY DISTRIBUTION MATRIX SELECT:
0 – Selects Matrix 1
1 – Selects Matrix 2
13:12 — Reserved – Must be written with 0b11
11:8 THBS
TMED HORIZONTAL BEAT SUPPRESSION:
Specifies the column shift value.