5 interrupt identification register (iir) – Intel PXA26X User Manual
Page 598
17-14
Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
Note:
To ensure that the DMA controller and programmed I/O do not access the same FIFO, software
must not set the DMAE while the TIE or RAVIE bits are set to a 1.
17.5.5
Interrupt Identification Register (IIR)
The UART prioritizes interrupts in four levels (see
Table 17-7, “Interrupt Conditions”
) and records
them in the IIR. The IIR stores information that indicates that a prioritized interrupt is pending and
identifies the source of the interrupt. The Interrupt Identification Register (IIR) bit definitions are
shown in
If additional data is received before a receiver time out interrupt is serviced, the interrupt is
deasserted.
Read IIR to determine the type and source of UART interrupts. To be 16550 compatible, the lower
4 bits of the IIR are priority encoded, shown in
Table 17-9, “Interrupt Identification Register
. If two or more interrupts represented by these bits occur, only the interrupt
with the highest priority is displayed. The auto-baud lock interrupt is not priority encoded. It
asserts/deasserts independently of the lower 4 bits.
IIR[nIP] indicates the existence of an interrupt in the lower four bits of the IIR. A low signal on this
bit indicates an encoded interrupt is pending. If this bit is high, no encoded interrupt is pending,
regardless of the state of the other 3 bits. nIP has no effect or association with IIR[ABL], which
asserts/deasserts independently of nIP.
3
R/W
MIE
MODEM INTERRUPT ENABLE (Source IIR[IID]):
0 – Modem Status Interrupt disabled
1 – Modem Status Interrupt enabled
2
R/W
RLSE
RECEIVER LINE STATUS INTERRUPT ENABLE (Source IIR[IID]):
0 – Receiver Line Status Interrupt disabled
1 – Receiver Line Status Interrupt enabled
1
R/W
TIE
TRANSMIT DATA REQUEST INTERRUPT ENABLE (Source IIR[IID]):
0 – Transmit FIFO data request interrupt disabled
1 – Transmit FIFO data request interrupt enabled
0
R/W
RAVIE
RECEIVER DATA AVAILABLE INTERRUPT ENABLE (Source IIR[IID]):
0 – Receiver data available (trigger threshold reached)
interrupt
disabled
1 – Receiver data available (trigger threshold reached) interrupt enabled
Table 17-6.
IER Bit Definitions (Sheet 2 of 2)
Physical Address
0x4160_0004
Interrupt Enable Reg. (IER)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
DM
AE
UU
E
NRZ
E
RT
OI
E
MI
E
RL
SE
TIE
RA
VI
E
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
Bits
Access
Name
Description