Intel PXA26X - Manual (Page 268)

6-78 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
11. Optionally, in systems that contain SDRAM or synchronous static memory, enable auto-
power-down by setting MDREFR:APD.
6.13 General Purpose Input/Output Reset Procedure
On a GPIO Reset, the Memory Controller registers keep the values they had before the reset. No
new configuration programming is required. However, SDRAM refreshes do not occur during the
reset time. After nRESET_OUT is deasserted, the memory controller will continue refreshing. By
ensuring a refresh time for SDRAM that is smaller than the default, it is possible to preserve the
SDRAM contents. To do this, follow this procedure:
1. The SDRAM refresh time is chosen by taking the specified refresh time, typically 64 ms, and
subtracting the GPIO reset time (found in the Intel® PXA26x Processor Family Electrical,
Mechanical and Thermal Specifications). For example, the GPIO reset time is ~360
microseconds, leaving an SDRAM refresh time of (64 ms - .360 ms) = 63.64 ms. Use this time
to program the MDREFR[DRI].
2. In the boot code, determine the type of reset. If the reset was a GPIO reset, then refresh all the
SDRAM rows. Refreshing all the SDRAM rows preserves their value in case GPIO reset
occurs again.
3. After all the SDRAM rows have been refreshed, enable GPIO reset.