10 power on reset and boot operation, 11 power management – Intel PXA26X User Manual
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2-8
Intel® PXA26x Processor Family Developer’s Manual
System Architecture
Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.
Register space, where a register is not specifically mapped, is defined as reserved space. Reading
or writing reserved space causes unpredictable results.
The processor does not use all register bit locations. The unused bit locations are marked reserved
and are allocated for future use. Write reserved bit locations as zeros. Ignore the values of these bits
during reads because their states are unpredictable.
2.9
Selecting Peripherals vs. General Purpose Input/
Output
Most peripherals connect to the external pins through GPIOs. To use a peripheral connected
through a GPIO, the software must first configure the GPIO so that the desired peripheral is
connected to its pins. The default state for most of the pins is GPIO inputs. Some of the GPIOs
default to their alternate function and do not need to be configured for use.
To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral
function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have
multiple alternate functions. After a function is selected for a pin, all other functions are excluded.
For this reason some peripherals are mapped to multiple GPIOs, as shown in
Alternate Functions” on page 4-3
. Multiple mapping does not mean multiple instances of a
peripheral – only that the peripheral is connected to the pins in several ways.
2.10
Power on Reset and Boot Operation
Before the device using the processor is powered on, the system must assert nRESET and nTRST.
To allow the internal clocks to stabilize, all power supplies must be stable for a specified period
before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is driven
active and can be used to reset other devices in the system. For additional information, see the
Intel® PXA26x Processor Family Design Guide.
When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attempts to boot from physical address location 0x0000 0000,
located in flash.
The BOOT_SEL[2:0] pins are sampled when reset is deasserted. The PXA26x processor family
version defines the BOOT_SEL[2:0] pins configuration.
2.11
Power Management
The processor offers a number of modes to manage system power. These range widely in level of
power savings and level of functionality. These modes are supported:
•
Turbo mode – low latency (nanoseconds) switch between two preprogrammed frequencies
•
Run mode – normal full function mode
•
Idle mode – core clocks are stopped – resume through an interrupt