10 modem status register (msr) – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
10-19
Universal Asynchronous Receiver/Transmitter
10.4.2.10
Modem Status Register (MSR)
The MSR provides the current state of the control lines from the modem or data set (or a peripheral
device emulating a modem) to the processor. In addition to this current state information, four bits
of the MSR provide change information. MSR[3:0] are set when a control input from the modem
changes state. They are cleared when the processor reads the MSR. Differences between UARTs
specific to this register are described in
Section 10.5.1, “UART Register Differences” on
The status of the modem control lines do not affect the FIFOs. To use these lines for flow control,
IER[MIE] must be set. When an interrupt on one of the flow control pins occurs, the interrupt
service routine must disable the UART. The UART continues transmission/reception of the current
character and then stops. The contents of the FIFOs is preserved. If the UART is re-enabled,
transmission continues where it stopped. Interrupts from the flow control pins will not come
through the UART unit if the unit is disabled. When disabling the unit because of flow control,
interrupts must be enabled in the processor interrupt controller for the flow control pins. The
interrupt controller still triggers interrupts if the pins are in alternate function mode.
2
OUT1
TEST BIT:
This bit is used only in Loopback mode. It is ignored otherwise.
0 – Force MSR[RI] to 0
1 – Force MSR[RI] to 1
1
RTS
REQUEST TO SEND:
0 – nRTS pin is 1
1 – nRTS pin is 0
0
DTR
DATA TERMINAL READY:
0 – nDTR pin is 1
1 – nDTR pin is 0
Table 10-14. Modem Control Register
–
MCR (Sheet 2 of 2)
Base+0x10
Modem Control Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
e
s
e
rved
LO
O
P
OU
T
2
OU
T
1
RT
S
DT
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Bits
Name
Description