Intel PXA26X - Manual (Page 239)

Intel® PXA26x Processor Family Developer’s Manual 6-49
Memory Controller
Figure 6-14. 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0:RDF = 4,
MSC0:RDN = 1, MSC0:RRR = 1)
0 1 2 3 4 5 6 7
00
0000
RRR*2+1 RDF+1
RDN+1 RDF+2 RDN+1 RDF+2
MEMCLK
nCS[0]
MA[25:5]
MA[4:2]
MA[1:0]
nADV(nSDCAS)
nOE
nWE
RDnWR
MD[31:0]
DQM[3:0]
nCS[1]