Load data byte to be transferred in the idbr, Clear icr[stop] bit, 3 read 1 byte as a master – Intel PXA26X User Manual
Page 358: To read 1 byte as a master, Read idbr data, Clear icr[stop] and icr[acknak] bits, Write a 1 to the isr[ite] bit to clear interrupt
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Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Bus Interface Unit
5. Write a 1 to the ISR[ALD] bit if set.
If the master loses arbitration, it performs an address retry when the bus becomes free. The
arbitration loss detected interrupt is disabled to allow the address retry.
6. Load data byte to be transferred in the IDBR.
7. Initiate the write.
Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[TB]
8. When an IDBR transmit empty interrupt occurs (unit is sending STOP).
Read ISR: IDBR transmit empty (1), unit busy (x), R/nW bit (0)
9. Write a 1 to the ISR[ITE] bit to clear the interrupt.
10. Clear ICR[STOP] bit.
9.6.3
Read 1 Byte as a Master
To read 1 byte as a master:
1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
2. Initiate the write.
Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
3. When an IDBR transmit empty interrupt occurs.
Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
4. Write a 1 to the ISR[ITE] bit to clear the interrupt.
5. Initiate the read.
Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]
6. When an IDBR receive full interrupt occurs (unit is sending STOP).
Read ISR: IDBR receive full (1), unit busy (x), R/nW bit (1), ACK/NAK bit (1)
7. Write a 1 to the ISR[IRF] bit to clear the interrupt.
8. Read IDBR data.
9. Clear ICR[STOP] and ICR[ACKNAK] bits
9.6.4
Write 2 Bytes and Repeated Start Read 1 Byte as a Master
To write 2 bytes and execute a repeated start to read 1 byte as a master:
1. Load target slave address and R/nW bit in the IDBR. R/nW must be 0 for a write.
2. Initiate the write.
Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
3. When an IDBR transmit empty interrupt occurs.
Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0)
4. Write a 1 to the ISR[ITE] bit to clear interrupt.
5. Load data byte to be transferred in the IDBR.
6. Initiate the write.
Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], set ICR[TB]