Intel PXA26X - Manual (Page 433)

Intel® PXA26x Processor Family Developer’s Manual 12-23
Universal Serial Bus Device Controller
12.6.1.7 Reset Interrupt Request (RSTIR)
The reset interrupt request register is set when the host issues a reset. When the host issues a reset,
the entire UDC is reset. The RSTIR bit retains its state so software can determine that the design
was reset. If REM is zero, RSTIR being set does not generate an interrupt but status continues to be
updated.
12.6.1.8 Reset Interrupt Mask (REM)
The reset interrupt mask (REM) masks or enables the reset interrupt request to the interrupt
controller. When REM is 1, the interrupt is masked and the setting of RSTIR does not generate an
interrupt. When REM is 0, the RSTIR setting generates an interrupt when the USB host controller
issues an UDC reset. Programming REM does not affect the state of RSTIR.
Appendix , “UDC Control Register” shows the location of the bits in UDC control register
(UDCCR). The UDE bit is cleared to zero, which disables the UDC following a core reset. Writes
to reserved bits are ignored and reads return zeros.
Table 12-12. UDC Control Register (Sheet 1 of 2)
0h 4060 0000 UDCCR Read/Write and Read-Only
Bit 31:8 7 6 5 4 3 2 1 0
Reserved REM RSTIR SRM SUSIR RESIR RSM UDA UDE
Rese
t
X 1 0 1 0 0 0 0 0
Bits Name Description
31:8 — Reserved for future use
7 REM
RESET INTERRUPT MASK.(read/write):
0 – Reset interrupt enabled.
1 – Reset interrupt disabled.
6 RSTIR
RESET INTERRUPT REQUEST (read/write 1 to clear):
1 – UDC was reset by the host.
5 SRM
Suspend/resume interrupt mask (read/write):
0 – Suspend/resume interrupt enabled.
1 – Suspend/resume interrupt disabled.
4 SUSIR
SUSPEND INTERRUPT REQUEST (read/write 1 to clear):
1 – UDC received, suspend signalling from the host.
3 RESIR
RESUME INTERRUPT REQUEST (read/write 1 to clear):
1 – UDC received, resume signalling from the host.