Intel PXA26X - Manual (Page 300)

7-32 Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
After the count has elapsed, the VSYNC (L_FCLK) signal is pulsed. EFW generates a wait period
ranging from 0 to 255 line clock cycles (EFW=0x00 disables the EOF wait count). L_LCLK does
not toggle during the generation of the EFW line clock periods.
In passive mode, set EFW to zero so that no EOF wait states are generated. Use VSW exclusively
in passive mode to insert line clock wait states. This lets the LCD controller’s DMAC fill the
palette and insert additional pixels before the start of the next frame.
7.6.3.3 Vertical Sync Pulse Width (VSW)
In active mode, the 6-bit vertical sync pulse width (VSW) field specifies the pulse width of the
vertical synchronization pulse or to add extra “dummy” line clock wait states between the end and
beginning of frame in passive mode.
In active mode (LCCR0[PAS]=1), L_FCLK generates the vertical sync signal and is asserted each
time the last line or row of pixels for a frame is sent to the display and a programmable number of
line clock wait states as specified by LCCR1[BLW] have elapsed. When L_FCLK is asserted, the
value in VSW is transferred to a 6-bit down counter, which uses the line clock frequency to
decrement. When the counter reaches zero, L_FCLK is negated. VSW can be programmed to
generate a vertical sync pulse width ranging from 1- to 64-line-clock periods. Program VSW with
the desired number of line clocks minus one. The polarity (active and inactive state) of the
L_FCLK pin is programmed using the vertical sync polarity (VSP) bit in LCCR3.
In passive mode (LCCR0[PAS]=0), VSW does not affect the timing of the L_FCLK pin, but rather
can be used to add extra line clock wait states between the end of each frame and the beginning of
the next frame. When the last line clock of a frame is negated, the value in VSW is transferred to a
6-bit down counter that uses the line clock frequency to decrement. When the counter reaches zero,
the next frame begins. Program VSW to generate from 1- to 64-dummy-line-clock periods between
each frame in passive mode. Program VSW to allow:
• Enough wait states to occur between frames such that the LCD’s DMAC is able to fully load
the on-chip palette (if applicable)
• A sufficient number of encoded pixel values to be fetched from the frame buffer, to be
processed by the dither logic and placed in the output FIFO, ready to be sent to the LCD data
pins.
The number of wait states required is system dependent, depending on such factors as:
• Palette buffer size (0, 8, 32, or 512 bytes)
• Memory system speed (number of wait states, burst speed, number of beats)
• Palette DMA request delay, LCCR0[PDD].
The line clock pin does toggle during the insertion of the line clock wait state periods.
VSW does not affect generation of the frame clock signal in passive mode. Passive LCD displays
require that the frame clock be active on the rising edge of the first line clock pulse of each frame,
with adequate setup and hold time. To meet this requirement, the LCD controller’s frame clock pin
is asserted on the rising edge of the first pixel clock for each frame. The frame clock remains
asserted for the remainder of the first line as pixels are sent to the display. It is then negated on the
rising edge of the first pixel clock of the second line of each frame.