1 lcd controller control register 0 (lccr0), Section 7.6.1 – Intel PXA26X User Manual
Page 288
7-20
Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
An additional control field exists to tune the DMAC’s performance based on the type of memory
system implemented with the processor. This field controls the placement of a minimum delay
between each LCD-DMA-request-during-palette loads to insure enough bus bandwidth is given to
other bus masters accesses.
The DMA descriptor addresses are initially programmed by software. After that, the other DMA
registers are programmed by the hardware.
provides a complete description of how
the DMA is programmed.
The status registers contain bits that signal:
•
Input and output FIFO overrun and underrun errors
•
DMA bus errors
•
When the DMAC starts and ends a frame
•
When the last active frame has completed after the LCD is disabled
•
Each time the L_BIAS pin has toggled a programmed number of times
Each of these hardware-detected events can signal an interrupt request to the interrupt controller.
7.6.1
LCD Controller Control Register 0 (LCCR0)
shows the bit layout for LCD Control Register 0. This register is read/write. The control
bits within all other control registers must be programmed before setting ENB=1 (a word write can
be used to configure LCCR0 while setting ENB after all other control registers have been
programmed). The LCD controller must be disabled when changing the state of any control bit
within the LCD controller. Reserved bits must be written with zeros. Ignore reads from reserved
bits.
Table 7-2. LCD Controller Control Register 0 (Sheet 1 of 3)
Physical Address
0x4400_0000
LCD Controller Control Register 0
LCD Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
v
e
d
OU
M
BM
PDD
QD
M
DI
S
DP
D
R
eser
v
e
d
PA
S
EF
M
IU
M
SF
M
LD
M
SD
S
CM
S
EN
B
Reset
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:22
—
Reserved
21
OUM
OUTPUT FIFO UNDERRUN MASK (
):
0 – FIFO underrun errors generate an interrupt.
1 – FIFO underrun errors do not generate an interrupt.
20
BM
BRANCH MASK (
0 – Generates an interrupt after branching to a new frame.
1 – Branch Start (BS) condition does not generate an interrupt.