Intel PXA26X - Manual (Page 611)

Intel® PXA26x Processor Family Developer’s Manual 17-27
Hardware UART
Table 17-16. MCR Bit Definitions (Sheet 1 of 2)
Physical Address
0x4160_0010
Modem Control Reg. (MCR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
AF
E
LO
O
P
OU
T
2
R
e
s
e
rved
RT
S
R
e
s
e
rved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? 0 ?
Bits Access Name Description
31:8 N/A — Reserved – Read as unknown and must be written as zero.
5 R/W AFE
AUTOFLOW CONTROL ENABLE:
0 – Auto-RTS and auto-CTS are disabled.
1 – Auto-CTS is enabled. If MCR[RTS] is also set, both auto-CTS and
auto-RTS is enabled.
4 R/W LOOP
LOOPBACK MODE:
This bit provides a local loopback feature for diagnostic testing of the UART.
When LOOP is set to a logic 1, this occurs: The transmitter serial output is
set to a logic 1 state. The receiver serial input is disconnected from the pin.
The output of the Transmitter Shift Register is “looped back” into the
Receiver Shift Register input. The four modem control inputs (nCTS, nDSR,
nDCD, and nRI) are disconnected from the pins and the modem control
output pins (nRTS and nDTR) are forced to their inactive state.
Coming out of the loopback mode may result in unpredictable activation of
the delta bits (bits 3:0) in the Modem Status Register. It is recommended
that MSR is read once to clear the delta bits in the MSR.
Loopback mode must be configured before the UART is enabled.
MCR[RTS] is connected to the Modem Status Register CTS bit: This allows
software to test CTS functionality by setting or clearing MCR[RTS]
• RTS = 1 forces CTS to a 1
• RTS = 0 forces CTS to a 0
In loopback mode, data that is transmitted is immediately received. This
feature allows the processor to verify the transmit and receive data paths of
the UART. The transmit, receive and modem control interrupts are
operational, except the modem control interrupts are activated by MCR bits,
not the modem control pins. A break signal can also be transferred from the
transmitter section to the receiver section in loopback mode.
0 – normal UART operation
1 – loopback mode UART operation
3 R/W OUT2
OUT2 SIGNAL CONTROL:
OUT2 connects the UART’s interrupt output to the Interrupt Controller unit.
When LOOP = 0:
0 – UART interrupt is disabled
1 – UART interrupt is enabled.
When LOOP = 1, interrupts always go to the processor.