Intel PXA26X - Manual (Page 400)

11-6 Intel® PXA26x Processor Family Developer’s Manual
Fast Infrared Communication Port
If the data field contains any invalid chips (such as 0011, 1010, 1110) the frame aborts and the
oldest byte in the temporary FIFO is moved to the receive FIFO, the remaining temporary FIFO
entries are discarded, the end-of-frame (EOF) tag is set in the FIFO entry that holds the last valid
byte of data, and the receiver logic searches for the preamble.
The receive logic continuously searches for the 8-chip stop flag. When the stop flag is recognized,
the last byte that was placed within the receive FIFO is flagged as the frame’s last byte and the data
in the temporary FIFO is removed and used as the CRC value for the frame. The receive logic
compares the frame’s CRC value to the CRC-32 value, which is continuously calculated from the
incoming data stream. If CRC and CRC-32 values do not match, the last byte that was placed in the
receive FIFO is also tagged with a CRC error. The frame’s CRC value is not placed in the receive
FIFO. If the stop flag is not properly detected, an abort is signalled.
If software disables the FICP’s receiver while it is operating, the data byte being received stops
immediately, the serial shifter and receive FIFO are cleared, the System Integration Unit (SIU)
takes control of the receive data pin, and the clocks used by the receive logic are shut off to
conserve power. The receive data input polarity must be reprogrammed if the receive data pin is
used as a GPIO input.
11.2.9 Transmit Operation
Before it enables the FICP for transmission, the software can either preload the transmit FIFO by
filling it with data or allow service requests to cause the CPU or DMA to fill the FIFO after the
FICP is enabled. When the FICP is enabled, the transmit logic issues a service request if its FIFO
requires more data.
A minimum of 16 preambles are transmitted for each frame. If data is not available after the
sixteenth preamble, additional preambles are transmitted until a byte of valid data resides in the
bottom of the transmit FIFO. The preambles are followed by the start flag and the data from the
transmit FIFO. Groups of four chips (eight bits) are encoded and loaded in a serial shift register.
The contents of the serial shift register are sent out on the transmit data pin, which is clocked by the
8-MHz baud clock. The preamble, start and stop flags, and CRC value are transmitted
automatically.
When the transmit FIFO has 32 or more empty entries, an interrupt (if enabled) and DMA service
request are sent. If new data does not arrive quickly enough to prevent the FIFO from becoming
empty, the transmit logic attempts to transfer additional data from the empty FIFO. Software
determines whether to interpret the data underrun (a lack of data) as a signal of normal frame
completion or as an unexpected frame termination.
When software selects normal frame completion and an underrun occurs, the transmit logic
transmits the CRC value that was calculated during data transmission, including the address and
control bytes, followed by the stop flag that marks the end of the frame. The transmitter then
continuously transmits preambles until data is available in the FIFO. When data is available, the
transmitter starts to transmit the next frame.
When software selects unexpected frame termination and an underrun occurs, the transmit logic
transmits an abort and interrupts the CPU. The transmitter continues to send the abort until data is
available in the transmit FIFO. When data is available, the FICP transmits 16 preambles and a start
flag and starts the new frame. The off-chip receiver can choose to ignore the abort and continue to
receive data or signal the FICP to attempt to transmit the aborted frame again.