Intel PXA26X - Manual (Page 110)

4-2 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
Validate each GPIO pin’s state by reading the GPIO Pin Level Register (GPLR). You can read this
register any time to confirm the state of a pin. In addition, use the GPIO Rising Edge Detect Enable
Register (GRER) and GPIO Falling Edge Detect Enable Register (GFER) to detect either a rising
edge or falling edge on each GPIO pin. Use the GPIO Edge Detect Status Register (GEDR) to read
edge detect state. You may program these edge detects to generate interrupts (see
Section 4.2,
“Interrupt Controller” ). Also use GPIO[15:0] to generate wake-up events that bring the PXA26x
processor family out of sleep mode (refer to Section 3.4.9.5, “Exiting Sleep Mode” on page 3-19 ).
When the processor enters sleep mode, the contents of the Power Manager Sleep State registers
(PGSR0, PGSR1 and PGSR2) are loaded into the output data registers. If the particular pin is
programmed as an output, then the value in the PGSR is driven onto the pin before entering sleep
mode. When the processor exits sleep mode, these values remain driven until the GPIO pins are
reprogrammed by writing to the GPDR, GPSR or GPCR, and setting the GPIO bit in the Power
Manager Sleep Status Register (PSSR) to indicate that the GPIO registers have been re-initialized
after sleep mode. This is necessary since the GPIO logic loses power during sleep mode.
GPIOs[89:86] default to their dedicated functionality immediately on exiting sleep.
Most GPIO pins can also serve an alternate function within the processor. Certain modes within the
serial controllers and LCD controller require extra pins. These functions are hardwired into specific
GPIO pins and their use is described in the following paragraphs. Even though a GPIO pin is used
for an alternate function, you must still program the proper direction of that pin through the GPDR.
Details on alternate functions are provided in
Section 4.1.2, “GPIO Alternate Functions” . Figure
4-1 shows a block diagram of a single GPIO pin.
Figure 4-1. General-Purpose I/O Block Diagram
Edge
Detect
GPIO Pin
Pin Direction
Register
Pin Set and
Clear Registers
Edge Detect
Status Register
Pin-Level
Register
0
Alternate Function
Registers
Rising Edge Detect
Enable Register
Falling Edge Detect
Enable Register
1
2
3
Alternate Functions
(Outputs)
Alternate Functions
(Inputs)
0
1
2
3
Power Manager
Sleep Wake-up logic
2