Intel PXA26X - Manual (Page 224)

6-34 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
7:5 SXRL0
RAS LATENCY FOR SYNCHRONOUS STATIC (SX) MEMORY PARTITION PAIR 0/1:
Number of external SDCLK cycles between reception of the ACT command and reception
of the READ command. The unit size for SXRL0 is the external SDCLK cycle.
IF SXTP0 = 00 (SMROM):
000 – 1 clock
001 – 2 clocks
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – 7 clocks
111 – 8 clocks
IF SXTP0 = 10 (non-SDRAM timing fast flash), this field is not used and must be
programmed to 111
4:2 SXCL0
CAS LATENCY FOR SX MEMORY PARTITION PAIR 0/1:
Number of external SDCLK cycles between reception of the READ command and latching
of the data. The unit size for SXCL0 is the external SDCLK cycle. When SX Memory is run
at half the memory clock frequency (MDREFR:K0DB2 = 1), the delay is 2*MEMCLK When
in doubt as to which CAS Latency to use, the next larger must be used.
IF SXTP0 = 00 (SMROM):
000 – Reserved
001 – Reserved
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – Reserved
111 – Reserved
IF SXTP0 = 10 (non-SDRAM timing fast flash)
000 – Reserved
001 – Reserved
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – 7 clocks
111 – Reserved
Table 6-14. SXCNFG Register Bitmap (Sheet 5 of 6)
4800 001C SXCNFG
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
eser
ved
S
X
LA
TC
H
2
SXTP
2
SX
C
A
2
SX
R
A
2
SXR
L2
SXC
L2
S
XEN
2
R
eser
ved
S
X
LA
TC
H
0
SXTP
0
SX
C
A
0
SX
R
A
0
SXR
L0
SXC
L0
S
XEN
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * 0 *
Bits Name Description