9 multiple block read, 10 stream write, Set mmc_i_mask to 0x1e – Intel PXA26X User Manual
Page 531: Wait for mmc_i_reg[data_tran_done] interrupt
Intel® PXA26x Processor Family Developer’s Manual
15-19
MultiMediaCard Controller
The multiple block write mode also requires a stop transmission command, CMD12, after the data
is transferred to the card. After the MMC_I_REG[DATA_TRAN_DONE] interrupt occurs, the
software must program the controller registers to send a stop data transmission command.
15.4.9
Multiple Block Read
The multiple block read mode is similar to the single block read mode, except that multiple blocks
of data are transferred. Each block is the same length. All the registers are set as they are for the
single block read, except that the MMC_NOB register is set to the number of blocks to be read.
The multiple block read mode requires a stop transmission command, CMD12, after the data from
the card is received. After the MMC_I_REG[DATA_TRAN_DONE] interrupt has occurred, the
software must program the controller registers to send a stop data transmission command.
15.4.10
Stream Write
In a stream write command, the software must stop the clock and set the registers as described in
section
Section 15.4.4, “No Data Command and Response Sequence”
. The following registers
must be set before the clock is started:
•
Set MMC_NOB register to ffffh.
•
Set MMC_BLKLEN register to the number of bytes per block.
•
Update MMC_CMDAT register as follows:
— Write 0b01 to the MMC_CMDAT[RESPONSE_FORMAT].
— Set the MMC_CMDAT[DATA_EN] bit.
— Set the MMC_CMDAT[WRITE/READ] bit.
— Set the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
•
Turn the clock on.
After it turns the clock on, the software must perform the following steps:
1. Wait for the response as described in section
Section 15.4.4, “No Data Command and
.
2. Write data to the MMC_TXFIFO FIFO and continue until all of the data is written to the FIFO.
Note:
When data less than 32 bytes is written to the FIFO, the MMC_PRTBUF[BUF_PART_FULL] bit
must be set.
3. Set MMC_I_MASK to 0x77 and wait for MMC_I_REG[STOP_CMD] interrupt.
4. Set the command registers for a stop transaction command (CMD12).
5. Wait for a response to the stop transaction command as described in section
“No Data Command and Response Sequence”
.
6. Set MMC_I_MASK to 0x1e.
7. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.