Intel PXA26X - Manual (Page 163)

Intel® PXA26x Processor Family Developer’s Manual 5-5
Direct Memory Access Controller
• Set zero
• Set three
The pattern repeats for the next eight channel services. In each set, the channels are given round-
robin priority.
The state machine used to determine the priority of the DMA channels is shown in Table 5-3 . Use
this table to determine the exact sequence the DMA controller gives to each channel when not all
channels are running concurrently.
The channels get a round-robin priority in each set. Out of reset, the state machine state is zero. If a
channel in set zero has a pending request, that channel is serviced. If a channel in set one has a
pending request, that channel is serviced and so on. Once a request is serviced, the state machine
state is incremented, wrapping around from state machine state seven back to state machine state
zero. If there is no pending request, the state machine stays in the current state machine state until
there is a pending request. See
Table 5-4 for priority scheme examples.
Table 5-2. Channel Priority (if all channels are running concurrently)
Set Channels Priority Number of times served
0 0,1,2,3 Highest 4 / 8
1 4,5,6,7 Higher 2 / 8
2 8,9,10,11 Low 1 / 8
3 12,13,14,15 Low 1 / 8
Table 5-3. Channel Priority
State Machine
State
DMA Set Priority within each State Machine State
0 S0 > S1 > S2 > S3
1 S1 > S0 > S3 > S2
2 S0 > S1 > S2 > S3
3 S2 > S3 > S0 > S1
4 S0 > S1 > S2 > S3
5 S1 > S0 > S3 > S2
6 S0 > S1 > S2 > S3
7 S3 > S2 > S1 > S0
Table 5-4. Priority Schemes Examples
Channels Programmed DMA Channel Priority
ch0, ch1 0,1,0,1,0,1,0,1,etc.
ch0, ch15 0,0,0,15,0,0,0,15,etc.
ch0, ch4, ch8, ch12 0,4,0,8,0,4,0,12,etc.
ch0, ch1, ch8, ch12 0,1,0,8,0,1,0,12,etc.
ch0, ch4 0,4,0,0,0,4,0,4,etc.
ch8, ch12 8,12,8,8,8,12,8,12,etc.